Description
EM68B16CWQD-25H Etron SDRAM DDR2 Memory IC 512MBIT (32M x 16) Commercial Temp. 1.8V SSTL_18 400 MHz 400 ps 84-FBGA RoHS
Product Attributes
Category Integrated Circuits (ICs)
Memory
Mfr Etron Technology, Inc.
Package Tape & Reel (TR)
Memory Type Volatile
Memory Format
DRAM
Technology
SDRAM – DDR2
Memory Size
512M (32M x 16)
Memory Interface
Parallel
Write Cycle Time – Word, Page
15ns
Voltage – Supply
1.7V ~ 1.9V
Operating Temperature
0C ~ 85C (TC)
Mounting Type
Surface Mount
Package / Case
84-TFBGA
Supplier Device Package
84-FBGA (8×12.5)
Clock Frequency
400 MHz
Access Time
400 ps
Base Product Number
EM68B16
The EM68B16C is a high-speed CMOS DoubleData-Rate-Two
(DDR2), synchronous dynamic randomaccess
memory (SDRAM) containing 512 Mbits in a 16-
bit wide data I/Os. It is internally configured as a quad
bank DRAM, 4 banks x 8Mb addresses x 16 I/Os.
The device is designed to comply with DDR2 DRAM
key features such as posted CAS# with additive latency,
Write latency = Read latency -1, Off-Chip Driver (OCD)
impedance adjustment, and On Die Termination(ODT).
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks. Inputs
are latched at the cross point of differential clocks (CK
rising and CK# falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS#) in a source
synchronous fashion. The address bus is used to convey
row, column, and bank address information in RAS #, CAS#
multiplexing style. Accesses begin with the registration
of a Bank Activate command, and then it is followed by
a Read or Write command. Read and write accesses to
the DDR2 SDRAM are 4 or 8-bit burst oriented; accesses
start at a selected location and continue for a programmed
number of locations in a programmed sequence. Operating
the four memory banks in an interleaved fashion allows
random access operation to occur at a higher rate than
is possible with standard DRAMs. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst sequence.
A sequential and gapless data rate is possible depending
on burst length, CAS latency, and speed grade of the
device.
Manufacturer:Electronic Components
Datasheet:EM68B16CWQK_Rev 1.1.pdf
