Description
TI – 74ALS112AN Dual J-K negative edge-triggered flip-flopDual Neg-Edge-Trig J-K Flip-Flop
SPECIFICATIONS
| Mfr Package Description | ROHS COMPLIANT,PLASTIC, DIP-16 |
| REACH Compliant | Yes |
| EU RoHS Compliant | Yes |
| China RoHS Compliant | Yes |
| Status | Active |
| Logic IC Type | J-K FLIP-FLOP |
| Sub Category | FF/Latches |
| Family | ALS |
| fmax-Min | 30.0 MHz |
| JESD-30 Code | R-PDIP-T16 |
These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE ) or clear (CLR ) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock p ulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
Manufacturer Part Number: 74ALS112AN
Texas Instruments
