AVX_Capacitors_High_voltage_MLC_Chips_600V

High Voltage MLC Chips

For 600V to 5000V Application

1808

271

HOW TO ORDER

DIMENSIONS

millimeters (inches)

AVX

Voltage Temperature

Capacitance Code

Capacitance

Test

Termination*

Style

600V = C

Coefficient

(2 significant digits

Tolerance

Level

1 = Pd/Ag

1206

1000V = A

C0G = A

+ no. of zeros)

C0G: J = ±5%

A = Standard

T = NiGuard

1210

1500V = S

X7R = C

Examples:

K = ±10%

Nickel

1808

2000V = G

10 pF = 100

M = ±20%

Barrier

1812

2500V = W

100 pF = 101

X7R: K = ±10%

Solderable

1825

3000V = H

1,000 pF = 102

M = ±20%

Plate

2220

4000V = J

22,000 pF = 223

Z = +80%, -20%

2225

5000V = K

220,000 pF = 224

3640

1 µF = 105

SIZE

1206

1210

1808*

1812*

1825*

2220*

2225*

3640*

(L) Length

3.20 ± 0.2

4.57 ± 0.25

4.50 ± 0.3

5.7 ± 0.4

5.72 ± 0.25

9.14 ± 0.25

(0.126 ± 0.008) (0.126 ± 0.008) (0.180 ± 0.010) (0.177 ± 0.012) (0.177 ± 0.012) (0.224 ± 0.016) (0.225 ± 0.010) (0.360 ± 0.010)

(W) Width

1.60 ± 0.2

2.50 ± 0.2

2.03 ± 0.25

3.20 ± 0.2

6.40 ± 0.3

5.0 ± 0.4

6.35 ± 0.25

10.2 ± 0.25

(0.063 ± 0.008) (0.098 ± 0.008) (0.080 ± 0.010) (0.126 ± 0.008) (0.252 ± 0.012) (0.197 ± 0.016) (0.250 ± 0.010) (0.400 ± 0.010)

(T) Thickness

1.52

1.70

2.03

2.54

3.3

2.54

Max.

(0.060)

(0.067)

(0.080)

(0.100)

(0.130)

(0.100)

(t) terminal

min.

0.25 (0.010)

0.76 (0.030)

max.

0.75 (0.030)

1.02 (0.040)

1.52 (0.060)

High value, low leakage and small size are difficult parameters to obtain in
capacitors for high voltage systems. AVX special high voltage MLC chips
capacitors meet these performance characteristics and are designed for
applications such as snubbers in high frequency power converters,
resonators in SMPS, and high voltage coupling/DC blocking. These high
voltage chip designs exhibit low ESRs at high frequencies.

Larger physical sizes than normally encountered chips are used to make
high voltage chips. These larger sizes require that special precautions be
taken in applying these chips in surface mount assemblies. This is due
to differences in the coefficient of thermal expansion (CTE) between the
substrate materials and chip capacitors. Apply heat at less than 4°C per
second during the preheat. The preheat temperature must be within 50°C
of the peak temperature reached by the ceramic bodies through the
soldering process. Chips 1808 and larger to use reflow soldering only.

Capacitors with X7R Dielectrics are not intended for AC line filtering
applications. Contact plant for recommendations.

Capacitors may require protective surface coating to prevent external
arcing.

*Note:

Leaded terminations are available.
Styles 1825, 2225, & 3640 are available with “N”, “L” or “J” leads as seen on page 9.
“V” denotes uncoated leaded units similar to SM0 product.
“W” denotes leaded epoxy coated units similar to SM5 product.
IE 1825AA103KAV00J would be uncoated leaded part with “J” style leads.

*Reflow Soldering Only

Packaging

1 = 7" Reel
3 = 13" Reel
9 = Bulk

Special

Code

A = Standard

VOLTAGE

1206

1210

1808

1812

1825

2220

2225

3640

600

min.

10 pF

100 pF

1000 pF

max.

680 pF

1500 pF

2700 pF

5600 pF

0.012 µF

0.015 µF

0.047 µF

min.

10 pF

100 pF

1000 pF

1000

max.

470 pF

820 pF

1500 pF

2700 pF

6800 pF

0.010 µF

0.018 µF

min.

10 pF

100 pF

1500

max.

150 pF

330 pF

470 pF

1000 pF

2700 pF

3300 pF

8200 pF

min.

10 pF

100 pF

2000

max.

68 pF

150 pF

270 pF

680 pF

1800 pF

2200 pF

5600 pF

min.

—

10 pF

100 pF

2500

max.

—

150 pF

390 pF

1000 pF

1200 pF

3900 pF

min.

—

10 pF

100 pF

3000

max.

—

100 pF

330 pF

680 pF

820 pF

2200 pF

min.

—

10 pF

100 pF

4000

max.

—

39 pF

100 pF

220 pF

330 pF

1000 pF

min.

—

10 pF

5000

max.

—

680 pF

VOLTAGE

1206

1210

1808

1812

1825

2220

2225

3640

600

min.

1000 pF

0.01 µF

max.

0.015 µF

0.033 µF

0.056 µF

0.10 µF

0.18 µF

0.22 µF

0.56 µF

min.

100 pF

1000 pF

0.01 µF

1000

max.

5600 pF

0.015 µF

0.018 µF

0.027 µF

0.10 µF

0.22 µF

min.

100 pF

1000 pF

1500

max.

1800 pF

3900 pF

6800 pF

0.012 µF

0.033 µF

0.039 µF

0.047 µF

0.068 µF

min.

10 pF

100 pF

1000 pF

2000

max.

1000pF

2200 pF

2700 pF

4700 pF

0.01 µF

0.015 µF

0.027 µF

min.

—

10 pF

100 pF

1000 pF

2500

max.

—

1800 pF

3300 pF

6800 pF

8200 pF

0.01 µF

0.022 µF

min.

—

10 pF

100 pF

1000 pF

3000

max.

—

1500 pF

2200 pF

4700 pF

6800 pF

0.018 µF

min.

—

100 pF

4000

max.

—

— —

—

6800

min.

—

100 pF

5000

max.

—

3300 pF

HIGH VOLTAGE C0G CAPACITANCE VALUES

HIGH VOLTAGE X7R MAXIMUM CAPACITANCE VALUES

X7R Dielectric

Performance Characteristics

Capacitance Range

10 pF to 0.047 µF
(25°C, 1.0 ±0.2 Vrms at 1kHz, for

≤

1000 pF use 1 MHz)

Capacitance Tolerances

±5%, ±10%, ±20%

Dissipation Factor

0.1% max. (+25°C, 1.0 ±0.2 Vrms, 1kHz, for

≤

1000 pF use 1 MHz)

Operating Temperature Range

-55°C to +125°C

Temperature Characteristic

0 ±30 ppm/°C (0 VDC)

Voltage Ratings

600, 1000, 1500, 2000, 2500, 3000, 4000 & 5000 VDC (+125°C)

Insulation Resistance

(+25°C, at 500 VDC)

100K M

Ω

min. or 1000 M

Ω

- µF min., whichever is less

Insulation Resistance

(+125°C, at 500 VDC)

10K M

Ω

min. or 100 M

Ω

- µF min., whichever is less

Dielectric Strength

120% rated voltage for 5 seconds at 50 mA max. current

Performance Characteristics

Capacitance Range

10 pF to 0.56 µF (25°C, 1.0 ±0.2 Vrms at 1kHz)

Capacitance Tolerances

±10%; ±20%; +80%, -20%

Dissipation Factor

2.5% max. (+25°C, 1.0 ±0.2 Vrms, 1kHz)

Operating Temperature Range

-55°C to +125°C

Temperature Characteristic

±15% (0 VDC)

Voltage Ratings

600, 1000, 1500, 2000, 2500, 3000, 4000 & 5000 VDC (+125°C)

Insulation Resistance

(+25°C, at 500 VDC)

100K M

Ω

min. or 1000 M

Ω

- µF min., whichever is less

Insulation Resistance

(+125°C, at 500 VDC)

10K M

Ω

min. or 100 M

Ω

- µF min., whichever is less

Dielectric Strength

120% rated voltage for 5 seconds at 50 mA max. current

High Voltage MLC Chips

For 600V to 5000V Applications

C0G Dielectric

Table 1: EIA and MIL Temperature Stable and General

Application Codes

In specifying capacitance change with temperature for Class
2 materials, EIA expresses the capacitance change over an
operating temperature range by a 3 symbol code. The
first symbol represents the cold temperature end of the
temperature range, the second represents the upper limit of
the operating temperature range and the third symbol repre-
sents the capacitance change allowed over the operating
temperature range. Table 1 provides a detailed explanation of
the EIA system.

Effects of Voltage –

Variations in voltage have little effect

on Class 1 dielectric but does affect the capacitance and
dissipation factor of Class 2 dielectrics. The application of
DC voltage reduces both the capacitance and dissipation
factor while the application of an AC voltage within a
reasonable range tends to increase both capacitance and
dissipation factor readings. If a high enough AC voltage is
applied, eventually it will reduce capacitance just as a DC
voltage will. Figure 2 shows the effects of AC voltage.

Cap. Change vs. A.C. Volts

X7R

Figure 2

Capacitor specifications specify the AC voltage at which to
measure (normally 0.5 or 1 VAC) and application of the
wrong voltage can cause spurious readings.

Typical Cap. Change vs. Temperature

X7R

Figure 3

0VDC

-55 -35 -15 +5 +25 +45 +65 +85 +105 +125

Temperature Degrees Centigrade

Capacitance Change Percent

+20

+10

-10

-20

-30

12.5

37.5

Volts AC at 1.0 KHz

Capacitance Change Percent

MIL CODE

Symbol

Temperature Range

-55°C to +85°C

-55°C to +125°C

-55°C to +150°C

Symbol

Cap. Change

Zero Volts

Rated Volts

+15%, -15%

+15%, -50%

+15%, -15%

+15%, -40%

+22%, -56%

+22%, -66%

+15%, -15%

+15%, -25%

+30%, -70%

+30%, -80%

+20%, -20%

+20%, -30%

Temperature characteristic is specified by combining range and change
symbols, for example BR or AW. Specification slash sheets indicate the
characteristic applicable to a given style of capacitor.

EIA CODE

Percent Capacity Change Over Temperature Range

RS198

Temperature Range

-55°C to +125°C

-55°C to +85°C

-30°C to +85°C

+10°C to +85°C

Code

Percent Capacity Change

±3.3%

±4.7%

±7.5%

±10%

±15%

±22%

+22%, -33%

+22%, - 56%

+22%, -82%

EXAMPLE – A capacitor is desired with the capacitance value at 25°C
to increase no more than 7.5% or decrease no more than 7.5% from
-30°C to +85°C. EIA Code will be Y5F.

General Description

Effects of Time –

Class 2 ceramic capacitors change

capacitance and dissipation factor with time as well as
temperature, voltage and frequency. This change with time is
known as aging. Aging is caused by a gradual re-alignment
of the crystalline structure of the ceramic and produces an
exponential loss in capacitance and decrease in dissipation
factor versus time. A typical curve of aging rate for semi-
stable ceramics is shown in Figure 4.

If a Class 2 ceramic capacitor that has been sitting on the
shelf for a period of time, is heated above its curie point,
(125°C for 4 hours or 150°C for

⁄

hour will suffice) the part

will de-age and return to its initial capacitance and dissi-
pation factor readings. Because the capacitance changes
rapidly, immediately after de-aging, the basic capacitance
measurements are normally referred to a time period some-
time after the de-aging process. Various manufacturers use
different time bases but the most popular one is one day
or twenty-four hours after “last heat.” Change in the aging
curve can be caused by the application of voltage and
other stresses. The possible changes in capacitance due to
de-aging by heating the unit explain why capacitance changes
are allowed after test, such as temperature cycling, moisture
resistance, etc., in MIL specs. The application of high voltages
such as dielectric withstanding voltages also tends to de-age
capacitors and is why re-reading of capacitance after 12 or 24
hours is allowed in military specifications after dielectric
strength tests have been performed.

Typical Curve of Aging Rate

X7R

Figure 4

Effects of Frequency –

Frequency affects capacitance

and impedance characteristics of capacitors. This effect is
much more pronounced in high dielectric constant ceramic
formulation than in low K formulations. AVX’s SpiCalci
software generates impedance, ESR, series inductance,
series resonant frequency and capacitance all as functions
of frequency, temperature and DC bias for standard chip
sizes and styles. It is available free from AVX and can be
downloaded for free from AVX website: www.avx.com.

Effects of Mechanical Stress –

High “K” dielectric ceramic

capacitors exhibit some low level piezoelectric reactions
under mechanical stress. As a general statement, the piezo-
electric output is higher, the higher the dielectric constant of
the ceramic. It is desirable to investigate this effect before
using high “K” dielectrics as coupling capacitors in extreme-
ly low level applications.

Reliability –

Historically ceramic capacitors have been one

of the most reliable types of capacitors in use today.
The approximate formula for the reliability of a ceramic
capacitor is:

where

= operating life

= test temperature and

= test life

= operating temperature

= test voltage

in °C

= operating voltage

X,Y

= see text

Historically for ceramic capacitors exponent X has been
considered as 3. The exponent Y for temperature effects
typically tends to run about 8.

1 10 100 1000 10,000 100,000

Hours

Capacitance Change Percent

+1.5

-1.5

-3.0

-4.5

-6.0

-7.5

Characteristic Max. Aging Rate %/Decade

C0G (NP0)
X7R, X5R

None

A capacitor is a component which is capable of storing
electrical energy. It consists of two conductive plates (elec-
trodes) separated by insulating material which is called the
dielectric. A typical formula for determining capacitance is:

C =

.224 KA

= capacitance (picofarads)

= dielectric constant (Vacuum = 1)

= area in square inches

= separation between the plates in inches

(thickness of dielectric)

.224

= conversion constant

(.0884 for metric system in cm)

Capacitance –

The standard unit of capacitance is the

farad. A capacitor has a capacitance of 1 farad when 1
coulomb charges it to 1 volt. One farad is a very large unit
and most capacitors have values in the micro (10

-6

), nano

(10

-9

) or pico (10

-12

) farad level.

Dielectric Constant –

In the formula for capacitance given

above the dielectric constant of a vacuum is arbitrarily cho-
sen as the number 1. Dielectric constants of other materials
are then compared to the dielectric constant of a vacuum.

Dielectric Thickness –

Capacitance is indirectly propor-

tional to the separation between electrodes. Lower voltage
requirements mean thinner dielectrics and greater capaci-
tance per volume.

Area –

Capacitance is directly proportional to the area of the

electrodes. Since the other variables in the equation are
usually set by the performance desired, area is the easiest
parameter to modify to obtain a specific capacitance within
a material group.

Energy Stored –

The energy which can be stored in a

capacitor is given by the formula:

⁄

= energy in joules (watts-sec)

= applied voltage

= capacitance in farads

Potential Change –

A capacitor is a reactive component

which reacts against a change in potential across it. This is
shown by the equation for the linear charge of a capacitor:

ideal

dV
dt

where

= Current

= Capacitance

dV/dt

= Slope of voltage transition across capacitor

Thus an infinite current would be required to instantly
change the potential across a capacitor. The amount of
current a capacitor can “sink” is determined by the above
equation.

Equivalent Circuit –

A capacitor, as a practical device,

exhibits not only capacitance but also resistance and
inductance. A simplified schematic for the equivalent circuit is:

= Capacitance

= Inductance

= Series Resistance

= Parallel Resistance

Reactance –

Since the insulation resistance (R

) is

normally very high, the total impedance of a capacitor is:

Z =

2
S

+ (X

- X

)

where

= Total Impedance

= Series Resistance

= Capacitive Reactance =

= Inductive Reactance = 2

The variation of a capacitor’s impedance with frequency
determines its effectiveness in many applications.

Phase Angle –

Power Factor and Dissipation Factor are

often confused since they are both measures of the loss in
a capacitor under AC application and are often almost iden-
tical in value. In a “perfect” capacitor the current in the
capacitor will lead the voltage by 90°.

In practice the current leads the voltage by some other
phase angle due to the series resistance R

. The comple-

ment of this angle is called the loss angle and:

Power Factor (P.F.) = Cos

or Sine

Dissipation Factor (D.F.) = tan

for small values of

the tan and sine are essentially equal

which has led to the common interchangeability of the two
terms in the industry.

I (Ideal)

I (Actual)

Phase
Angle

Loss
Angle

General Description

Equivalent Series Resistance –

The term E.S.R. or

Equivalent Series Resistance combines all losses both series
and parallel in a capacitor at a given frequency so that the
equivalent circuit is reduced to a simple R-C series
connection.

Dissipation Factor –

The DF/PF of a capacitor tells what

percent of the apparent power input will turn to heat in the
capacitor.

Dissipation Factor

E.S.R.

fC) (E.S.R.)

The watts loss are:

Watts loss

fCV

) (D.F.)

Very low values of dissipation factor are expressed as their
reciprocal for convenience. These are called the “Q” or
Quality factor of capacitors.

Parasitic Inductance –

The parasitic inductance of capac-

itors is becoming more and more important in the decoupling
of today’s high speed digital systems. The relationship
between the inductance and the ripple voltage induced on
the DC voltage line can be seen from the simple inductance
equation:

V = L

The

seen in current microprocessors can be as high as

0.3 A/ns, and up to 10A/ns. At 0.3 A/ns, 100pH of parasitic
inductance can cause a voltage spike of 30mV. While this
does not sound very drastic, with the Vcc for microproces-
sors decreasing at the current rate, this can be a fairly large
percentage.
Another important, often overlooked, reason for knowing
the parasitic inductance is the calculation of the resonant
frequency. This can be important for high frequency, by-pass
capacitors, as the resonant point will give the most signal
attenuation. The resonant frequency is calculated from the
simple equation:

res

= 1

Insulation Resistance –

Insulation Resistance is the

resistance measured across the terminals of a capacitor and
consists principally of the parallel resistance R

shown in the

equivalent circuit. As capacitance values and hence the area
of dielectric increases, the I.R. decreases and hence the
product (C x IR or RC) is often specified in ohm farads or
more commonly megohm-microfarads. Leakage current is
determined by dividing the rated voltage by IR (Ohm’s Law).

Dielectric Strength –

Dielectric Strength is an expression of

the ability of a material to withstand an electrical stress.
Although dielectric strength is ordinarily expressed in volts, it
is actually dependent on the thickness of the dielectric and
thus is also more generically a function of volts/mil.

Dielectric Absorption –

A capacitor does not discharge

instantaneously upon application of a short circuit, but drains
gradually after the capacitance proper has been discharged.
It is common practice to measure the dielectric absorption
by determining the “reappearing voltage” which appears
across a capacitor at some point in time after it has been fully
discharged under short circuit conditions.

Corona –

Corona is the ionization of air or other vapors

which causes them to conduct current. It is especially
prevalent in high voltage units but can occur with low voltages
as well where high voltage gradients occur. The energy
discharged degrades the performance of the capacitor and
can in time cause catastrophic failures.

E.S.R.

Surface Mounting Guide

MLC Chip Capacitors

Component Pad Design

Component pads should be designed to achieve good
solder filets and minimize component movement during
reflow soldering. Pad designs are given for the most common
sizes of multilayer ceramic capacitors for both wave and
reflow soldering. The basis of these designs is:

• Pad width equal to component width. It is permissible to

decrease this to as low as 85% of component width but it
is not advisable to go below this.

• Pad overlap 0.5mm beneath component.

• Pad extension 0.5mm beyond components for reflow and

1.0mm for wave soldering.

Component Spacing

For wave soldering components, must be spaced sufficiently
far apart to avoid bridging or shadowing (inability of solder to
penetrate properly into small spaces). This is less important
for reflow soldering but sufficient space must be allowed to
enable rework should it be required.

Preheat & Soldering

The rate of preheat should not exceed 4°C/second to
prevent thermal shock. A better maximum figure is about
2°C/second.

For capacitors size 1206 and below, with a maximum
thickness of 1.25mm, it is generally permissible to allow a
temperature differential from preheat to soldering of 150°C.
In all other cases this differential should not exceed 100°C.

For further specific application or process advice, please
consult AVX.

Cleaning

Care should be taken to ensure that the capacitors are
thoroughly cleaned of flux residues especially the space
beneath the capacitor. Such residues may otherwise
become conductive and effectively offer a low resistance
bypass to the capacitor.

Ultrasonic cleaning is permissible, the recommended
conditions being 8 Watts/litre at 20-45 kHz, with a process
cycle of 2 minutes vapor rinse, 2 minutes immersion in the
ultrasonic solvent bath and finally 2 minutes vapor rinse.

≥

1mm (0.04)

≥

1.5mm (0.06)

≥

1mm (0.04)

Case Size

0805

3.00 (0.120)

1.00 (0.040)

1.25 (0.050)

1206

4.00 (0.160)

1.00 (0.040)

2.00 (0.090)

1.00 (0.040)

1.60 (0.060)

1210

4.00 (0.160)

1.00 (0.040)

2.00 (0.090)

1.00 (0.040)

2.50 (0.100)

*1808

5.60 (0.220)

1.00 (0.040)

3.60 (0.140)

1.00 (0.040)

2.00 (0.080)

*1812

5.60 (0.220)

1.00 (0.040)

3.60 (0.140)

1.00 (0.040)

3.00 (0.120)

*1825

5.60 (0.220)

1.00 (0.040)

3.60 (0.140)

1.00 (0.040)

6.35 (0.250)

*2220

6.60 (0.260)

1.00 (0.040)

4.60 (0.180)

1.00 (0.040)

5.00 (0.200)

*2225

6.60 (0.260)

1.00 (0.040)

4.60 (0.180)

1.00 (0.040)

6.35 (0.250)

*HQCC

6.60 (0.260)

1.00 (0.040)

4.60 (0.180)

1.00 (0.040)

6.35 (0.250)

*3640

10.67 (0.427)

1.52 (0.060)

7.62 (0.300)

1.52 (0.060)

10.16 (0.400)

*HQCE

10.67 (0.427)

1.52 (0.060)

7.62 (0.300)

1.52 (0.060)

10.16 (0.400)

SOLDER PAD DESIGN

millimeters (inches)

*AVX recommends reflow soldering only.

Surface Mounting Guide

MLC Chip Capacitors

APPLICATION NOTES

Storage

Good solderability is maintained for at least twelve months,
provided the components are stored in their “as received”
packaging at less than 40°C and 70% RH.

Solderability

Terminations to be well soldered after immersion in a 60/40
tin/lead solder bath at 235 ± 5°C for 2 ± 1 seconds.

Leaching

Terminations will resist leaching for at least the immersion
times and conditions shown below.

Recommended Soldering Profiles

General

Surface mounting chip multilayer ceramic capacitors
are designed for soldering to printed circuit boards or other
substrates. The construction of the components is such that
they will withstand the time/temperature profiles used in both
wave and reflow soldering methods.

Handling

Chip multilayer ceramic capacitors should be handled with
care to avoid damage or contamination from perspiration
and skin oils. The use of tweezers or vacuum pick ups
is strongly recommended for individual components. Bulk
handling should ensure that abrasion and mechanical shock
are minimized. Taped and reeled components provides the
ideal medium for direct presentation to the placement
machine. Any mechanical shock should be minimized during
handling chip multilayer ceramic capacitors.

Preheat

It is important to avoid the possibility of thermal shock during
soldering and carefully controlled preheat is therefore
required. The rate of preheat should not exceed 4°C/second
and a target figure 2°C/second is recommended. Although
an 80°C to 120°C temperature differential is preferred,
recent developments allow a temperature differential
between the component surface and the soldering temper-
ature of 150°C (Maximum) for capacitors of 1210 size and
below with a maximum thickness of 1.25mm. The user is
cautioned that the risk of thermal shock increases as chip
size or temperature differential increases.

Soldering

Mildly activated rosin fluxes are preferred. The minimum
amount of solder to give a good joint should be used.
Excessive solder can lead to damage from the stresses
caused by the difference in coefficients of expansion between
solder, chip and substrate. AVX terminations are suitable for
all wave and reflow soldering systems. If hand soldering
cannot be avoided, the preferred technique is the utilization of
hot air soldering tools.

Cooling

Natural cooling in air is preferred, as this minimizes stresses
within the soldered joint. When forced air cooling is used,
cooling rate should not exceed 4°C/second. Quenching
is not recommended but if used, maximum temperature
differentials should be observed according to the preheat
conditions above.

Cleaning

Flux residues may be hygroscopic or acidic and must be
removed. AVX MLC capacitors are acceptable for use with all
of the solvents described in the specifications MIL-STD-202
and EIA-RS-198. Alcohol based solvents are acceptable
and properly controlled water cleaning systems are also
acceptable. Many other solvents have been proven successful,
and most solvents that are acceptable to other components
on circuit assemblies are equally acceptable for use with
ceramic capacitors.

Wave

300

250

200

150

100

Solder T

emp.

(Preheat chips before soldering)
T/maximum 150

3 sec. max

1 to 2 min

Preheat

Natural

Cooling

230

250

Reflow

300

250

200

150

100

Solder T

emp.

10 sec. max

1min

(Minimize soldering time)

Natural

Cooling

220

250

Preheat

Termination Type

Solder

Immersion Time

Tin/Lead/Silver Temp. °C

Seconds

Nickel Barrier

60/40/0

260 ± 5

30 ± 1

Metric dimensions will govern.
English measurements rounded and for reference only.

MLC Chips

Packaging of Chip Components

TAPE & REEL QUANTITIES

All tape and reel specifications are in compliance with EIA481 or IEC-286-3.

8mm

12mm

24mm

0805
1206

1808

1812, 1825

3640

1210

2220, 2225, HQCC

HQCE

Qty. per Reel/7" Reel

2000

1000

N/A

Qty. per Reel/13" Reel

10,000

4000

1000

REEL DIMENSIONS

Tape

Size

Max.

Min.

Max.

+1.5

7.9 Min.

8mm

330

1.5

13.0±0.20

20.2

8.4 -0.0

14.4

(0.311)

(12.992)

(0.059)

(0.512±0.008)

(0.795)

(1.969)

(0.331 +.060)

(0.567)

10.9 Max.

-0.0

(0.429)

+2.0

11.9 Min.

12mm

330

1.5

13.0±0.20

20.2

12.4 -0.0

18.4

(0.469)

(12.992)

(0.059)

(0.512±0.008)

(0.795)

(1.969)

(0.488 +.079)

(0.724)

15.4 Max.

-0.0

(0.607)

+0.5

+2.0

23.9 Min.

24mm

360

1.5

13.0 -0.2

20.2

24.4 -0.0

30.4

(0.941)

(14.173)

(0.059)

(0.512 +.020)

(0.795)

(2.362)

(0.961 +.079)

(1.197)

27.4 Max.

-.008

-0.0

(1.079)

AUTOMATIC INSERTION PACKAGING

DIMENSIONS

millimeters (inches)