. Patented Technology
. Two HSTL differential outputs
. Two single LVTTL/LVCMOS inputs
. Operating frequency up to 300MHz with 15 pf load
. Very low output pin to pin skew < 30ps
. 3.2-ns propagation delay (max) 
. 2.4V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C 
. 14-pin TSSOP package 

The PO74HSTL85352A is a low-skew, 1-to-2 differential 
fanout buffer targeted to meet the requirements of 
high-performance clock and data distribution applications. 
The device is implemented on CMOS technology and has 
a fully differential internal architecture that is optimized to 
achieve low signal skews at operating frequencies of up to 
300MHz   . 

The device features two single-ended input paths that are 
multiplexed internally. This mux is controlled by the 
CLK_SEL pin. The PO74HSTL85352A functions as a 
signal-level translator and fanout on LVCMOS / LVTTL 
single-ended signal to two pair of HSTL differential loads. 
Since the PO74HSTL85352A introduces negligible jitter 
to the timing budget, it is the ideal choice for distributing 
high frequency, high precision clocks across back-planes 
and boards in communication systems. 

FEATURES:

Pin Configuration

Logic Block Diagram

DESCRIPTION:

CLK0

CLK1

Q0

nQ0

Q1

nQ1

0

1

CLK_EN

CLK_SEL

D

Q

LE

V

EE

CLK_EN

CLK_SEL

CLK0

V

EE

CLK1

V

CC

1

2

3

4

5

6

7

14

13

12

11

10

9

8

V

CC

Q0
nQ0
nc
Q1
nQ1
V

CC

LVCMOS Input to HSTL Output 1:2 Fanout Buffer

1

01/01/10

Potato Semiconductor Corporation

PO74HSTL85352A

www.potatosemi.com

300MHz TTL/CMOS Potato Chip

Control Input Function Table

Function Table

Pin Characteristics

Pin Definitions

Input clock select with pull down resistor

LVCMOS, LVTTL

LVCMOS, LVTTL

LVCMOS, LVTTL 

clock Input 

LVCMOS, LVTTL 

clock Input 

I,PD

GND

Power Ground

HSTL

HSTL

Complement output

Clock enabled

No connect

Power supply, positive connection

Power 

LVCMOS 

LVCMOS 

Ture output

s

t

u

p

n

s

I

t

u

p

t

u

O

N

E

_

K

L

L

C

E

S

_

K

L

e

C

c

r

u

o

S

d

e

t

c

e

l

e

1

S

Q

,

0

1

Q

Q

n

,

0

Q

n

0

0

0

K

L

W

C

O

L

;

d

e

l

b

a

si

H

D

G

I

H

;

d

e

l

b

a

si

D

1

1

0

K

L

W

C

O

L

;

d

e

l

b

a

si

H

D

G

I

H

;

d

e

l

b

a

si

D

0

0

1

K

L

d

C

e

l

b

a

n

d

E

e

l

b

a

n

E

1

1

1

K

L

d

C

e

l

b

a

n

d

E

e

l

b

a

n

E

s

t

u

p

n

s

I

t

u

p

t

u

O

1

K

L

C

r

o

0

K

L

1

C

Q

,

0

1

Q

Q

n

,

0

Q

n

0

W

O

H

L

G

I

H

H

1

G

I

W

H

O

L

l

o

b

m

y

S

r

e

t

e

m

a

r

a

s

P

n

o

it

i

d

n

o

C

t

s

e

m

T

u

m

i

n

i

M

l

a

c

i

p

y

T

m

u

m

i

x

a

M

s

ti

n

U

C

N

I

e

c

n

a

ti

c

a

p

a

C

t

u

p

n

I

F

4

p

R

P

U

L

L

U

P

r

o

t

si

s

e

R

p

u

ll

u

P

t

u

p

n

I

88
88

K
K

R

N

W

O

D

L

L

U

P

r

o

t

si

s

e

R

n

w

o

d

ll

u

P

t

u

p

n

I

VCC

VCC

Name

I/O

Type

Description

Pin

VEE

Q[0:1]#

Q[0:1]

NC

CLK_SEL
CLK_EN
CLK0

CLK1

I,PD
I,PU

I,PD

O

O

Power

7, 8,14

12, 9

13, 10

11
3

2

4

6
1, 5

LVCMOS Input to HSTL Output 1:2 Fanout Buffer

2

01/01/10

Potato Semiconductor Corporation

PO74HSTL85352A

www.potatosemi.com

300MHz TTL/CMOS Potato Chip

DC Electrical Characteristics

Symbol

Description

Test Conditions

Min

Typ

Max

Unit

V

OH

Output High voltage

Vcc=3V Vin=V

IH

or V

IL

, I

OH

= -12mA

2.4

3

-

V

V

OL

Output Low voltage

Vcc=3V Vin=V

IH

or V

IL

, I

OH

=12mA

-

0.3

0.5

V

V

IK

Clamp diode voltage

Vcc = Min. And

I

IN

= -18mA

-

-0.7

-1.2

V

Notes:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2.

Typical values are at Vcc = 3.3V, 25

°

C ambient.

3.

This parameter is guaranteed but not tested.

4.

Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

5.

VoH = Vcc – 0.6V at rated current

Maximum Ratings

Description

Max

Unit

Storage Temperature

-65 to 150

°

C

Operation Temperature

-40 to 85 

°

C

Operation Voltage

-0.5 to +4.6 

V

Input Voltage

-0.5 to +5.5 

V

Output Voltage

-0.5 to Vcc+0.5

V

Note:

stresses greater than listed under
Maximum

Ratings

may

cause

permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

LVCMOS Input to HSTL Output 1:2 Fanout Buffer

3

01/01/10

Potato Semiconductor Corporation

PO74HSTL85352A

www.potatosemi.com

300MHz TTL/CMOS Potato Chip

Power Supply Characteristics

Symbol

Description

Test Conditions (1)

Min

Typ

Max

Unit

Icc

Q

Quiescent Power Supply Current

Vcc=Max, Vin=Vcc or GND

-

0.1

30

uA

Notes:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, 25

°

C ambient.

3. This parameter is guaranteed but not tested.
4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

Switching Characteristics

t

i

n

U

x

a

M

)

1

(

s

n

o

i

t

i

d

n

o

C

t

s

e

T

n

o

i

t

p

i

r

c

s

e

D

l

o

b

m

y

S

t

PD

Propagation Delay CLKA or CLKB to Output pair

CL = 15pF

3.2

ns

tr/tf

Rise/Fall Time

0.8V – 2.0V

0.8

ns

tsk(o)

Output Pin to Pin Skew (Same Package)

ps
ps

tsk(pp)

Output Skew (Different Package)

fmax

F

p

5

1

=

L

C

y

c

n

e

u

q

e

r

F

t

u

p

n

I

250

MHz

Notes:

1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz

CL = 15pF, 125MHz

CL = 15pF, 125MHz

30

350

300

LVCMOS Input to HSTL Output 1:2 Fanout Buffer

4

01/01/10

Potato Semiconductor Corporation

PO74HSTL85352A

www.potatosemi.com

300MHz TTL/CMOS Potato Chip

Test Waveforms

FIGURE 2. 
HSTL OUTPUT

FIGURE 1. 
LVTTL/LVCMOS INPUT WAVEFORM DEFINITION

FIGURE 3. 
Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair

TPHL

TPLH
TPD

INPUT
CLOCK

OUTPUT
CLOCK

ANOTHER
OUTPUT
CLOCK

VO

tSK(O)

VO

tr,tf,
20-80%

Input

3V

1.5V

0V

FIGURE 4. 
CLK_EN Timing Diagram

Enabled

Disabled

CLK

CLK_EN

nQ0:nQ3

Q0:Q3

LVCMOS Input to HSTL Output 1:2 Fanout Buffer

5

01/01/10

Potato Semiconductor Corporation

PO74HSTL85352A

www.potatosemi.com

300MHz TTL/CMOS Potato Chip

Test Circuit

0.193

0.201

0.047

0.002

0.006

0.0256

typical

1

14

0.169

0.177

0.05

0.15

4.3

4.5

1.20

max.

4.90

5.10

0.65

0.19

0.30

0.007

0.012

Packaging Mechanical Drawing: 14 pin TSSOP

X.XX

X.XX

DENOTES DIMENSIONS

IN MILLIMETERS

SEATING PLANE

0.240

0.264

6.1

6.7

50Ohm

15pF

to

2pF

15pF

to

2pF

Vcc

Pulse

Generator

D.U.T

LVCMOS Input to HSTL Output 1:2 Fanout Buffer

6

01/01/10

Potato Semiconductor Corporation

PO74HSTL85352A

www.potatosemi.com

300MHz TTL/CMOS Potato Chip

LVCMOS Input to HSTL Output 1:2 Fanout Buffer

IC Ordering Information

Top-Marking

Ordering Code

Package

Pb-free & Green

PO74HSTL85352ASU for Tube
PO74HSTL85352ASR for Tape & Reel

PO74HSTL85352AS

-40

°

C to 85

°

C

-40

°

C to 85

°

C

TA

Pb-free & Green

14pin 173mil TSSOP

IC Package Information

PACKAGE

T

12

8

Top Left Corner

39 (12”)

3000

64 (20”)

96

14pin 173mil TSSOP

CODE

PACKAGE

TYPE

TAPE

WIDTH

TAPE TRAILER

TUBE

TAPE & REEL

LENGTH

TAPE

PITCH

QTY

LENGTH

TAPE LEADER

PER TAPE

QTY
PER

PIN 1 LOCATION

(mm)

(mm)

PO74HSTL85352AS

14pin 173mil TSSOP

7

01/01/10

Potato Semiconductor Corporation

PO74HSTL85352A

www.potatosemi.com

300MHz TTL/CMOS Potato Chip