Intel

®

 Quartus

®

 Prime Standard

Edition Handbook Volume 1

Design and Synthesis

Updated for Intel

®

 Quartus

®

 Prime Design Suite: 17.1

Subscribe
Send Feedback

QPS5V1 | 2017.10.06

Latest document on the web: 

PDF

 | 

HTML

Contents

1 Managing Intel

®

 Quartus

®

 Prime Projects..................................................................... 19

1.1 Understanding Intel Quartus Prime Projects..............................................................20
1.2 Viewing Basic Project Information........................................................................... 20

1.2.1 Viewing Project Reports............................................................................. 21
1.2.2 Viewing Project Messages.......................................................................... 22

1.3 Project Management Best Practices......................................................................... 23
1.4 Managing Project Settings......................................................................................25

1.4.1 Optimizing Project Settings........................................................................ 27

1.5 Managing Logic Design Files................................................................................... 29

1.5.1 Including Design Libraries.......................................................................... 30

1.6 Managing Timing Constraints..................................................................................31
1.7 Introduction to Intel FPGA IP Cores......................................................................... 31

1.7.1 IP Catalog and Parameter Editor................................................................. 32
1.7.2 Generating IP Cores (Intel Quartus Prime Standard Edition)............................39
1.7.3 Modifying an IP Variation........................................................................... 41
1.7.4 Upgrading IP Cores................................................................................... 41
1.7.5 Simulating Intel FPGA IP Cores................................................................... 47
1.7.6 Synthesizing IP Cores in Other EDA Tools..................................................... 58
1.7.7 Instantiating IP Cores in HDL......................................................................58

1.8 Integrating Other EDA Tools................................................................................... 59
1.9 Managing Team-based Projects............................................................................... 60

1.9.1 Preserving Compilation Results................................................................... 60
1.9.2 Factors Affecting Compilation Results...........................................................61
1.9.3 Migrating Compilation Results Across Intel Quartus Prime Software Versions..... 61
1.9.4 Archiving Projects..................................................................................... 62
1.9.5 Using External Revision Control...................................................................64
1.9.6 Migrating Projects Across Operating Systems................................................ 65

1.10 Scripting API...................................................................................................... 67

1.10.1 Scripting Project Settings......................................................................... 67
1.10.2 Project Revision Commands......................................................................67
1.10.3 Project Archive Commands....................................................................... 68
1.10.4 Project Database Commands.................................................................... 69
1.10.5 Project Library Commands........................................................................70

1.11 Document Revision History...................................................................................70

2 Design Planning with the Intel Quartus Prime Software................................................ 73

2.1 Design Planning with the Intel Quartus Prime Software.............................................. 73
2.2 Creating Design Specifications................................................................................ 73
2.3 Selecting Intellectual Property Cores....................................................................... 74
2.4 Using Platform Designer (Standard) and Standard Interfaces in System Design.............74
2.5 Device Selection................................................................................................... 75

2.5.1 Device Migration Planning.......................................................................... 76

2.6 Development Kit Selection..................................................................................... 76

2.6.1 Specifying a Development Kit for a New Project............................................ 76
2.6.2 Specifying a Development Kit for an Existing Project......................................77
2.6.3 Setting Pin Assignments............................................................................ 78

2.7 Planning for Device Programming or Configuration.................................................... 78

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

2

2.8 Estimating Power.................................................................................................. 78
2.9 Early Pin Planning and I/O Analysis......................................................................... 79

2.9.1 Simultaneous Switching Noise Analysis........................................................ 81

2.10 Selecting Third-Party EDA Tools.............................................................................82

2.10.1 Synthesis Tool........................................................................................ 82
2.10.2 Simulation Tool....................................................................................... 82
2.10.3 Formal Verification Tools...........................................................................82

2.11 Planning for On-Chip Debugging Tools....................................................................83
2.12 Design Practices and HDL Coding Styles................................................................. 84

2.12.1 Design Recommendations.........................................................................84
2.12.2 Recommended HDL Coding Styles............................................................. 84
2.12.3 Managing Metastability............................................................................ 85

2.13 Planning for Hierarchical and Team-Based Design.................................................... 85

2.13.1 Flat Compilation Flow with No Design Partitions...........................................86
2.13.2 Incremental Compilation with Design Partitions........................................... 86
2.13.3 Planning Design Partitions and Floorplan Location Assignments......................87

2.14 Running Fast Synthesis........................................................................................ 87
2.15 Document Revision History...................................................................................88

3 Intel Quartus Prime Incremental Compilation for Hierarchical and Team-Based

Design..................................................................................................................... 90
3.1 About Intel Quartus Prime Incremental Compilation...................................................90
3.2 Deciding Whether to Use an Incremental Compilation Flow......................................... 90

3.2.1 Flat Compilation Flow with No Design Partitions.............................................90
3.2.2 Incremental Compilation Flow With Design Partitions..................................... 91
3.2.3 Team-Based Design Flows and IP Delivery.................................................... 94

3.3 Incremental Compilation Summary......................................................................... 96

3.3.1 Incremental Compilation Single Intel Quartus Prime Project Flow.....................96
3.3.2 Steps for Incremental Compilation.............................................................. 96
3.3.3 Creating Design Partitions.......................................................................... 97

3.4 Common Design Scenarios Using Incremental Compilation......................................... 99

3.4.1 Reducing Compilation Time When Changing Source Files for One Partition........ 99
3.4.2 Optimizing a Timing-Critical Partition........................................................... 99
3.4.3 Adding Design Logic Incrementally or Working With an Incomplete Design......100
3.4.4 Debugging Incrementally With the Signal Tap Logic Analyzer.........................101
3.4.5 Functional Safety IP Implementation..........................................................102

3.5 Deciding Which Design Blocks Should Be Design Partitions........................................109

3.5.1 Impact of Design Partitions on Design Optimization..................................... 112
3.5.2 Design Partition Assignments Compared to Physical Placement Assignments... 113
3.5.3 Using Partitions With Third-Party Synthesis Tools......................................... 113
3.5.4 Assessing Partition Quality........................................................................114

3.6 Specifying the Level of Results Preservation for Subsequent Compilations................... 116

3.6.1 Netlist Type for Design Partitions............................................................... 116
3.6.2 Fitter Preservation Level for Design Partitions..............................................117
3.6.3 Where Are the Netlist Databases Saved?.................................................... 118
3.6.4 Deleting Netlists......................................................................................118
3.6.5 What Changes Initiate the Automatic Resynthesis of a Partition?....................118

3.7 Exporting Design Partitions from Separate Intel Quartus Prime Projects......................121

3.7.1 Preparing the Top-Level Design................................................................. 122
3.7.2 Project Management— Making the Top-Level Design Available to Other

Designers..............................................................................................123

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

3

3.7.3 Exporting Partitions................................................................................. 125
3.7.4 Viewing the Contents of a Intel Quartus Prime Exported Partition File (.qxp)... 126
3.7.5 Integrating Partitions into the Top-Level Design...........................................126

3.8 Team-Based Design Optimization and Third-Party IP Delivery Scenarios......................129

3.8.1 Using an Exported Partition to Send to a Design Without Including Source

Files..................................................................................................... 129

3.8.2 Creating Precompiled Design Blocks (or Hard-Wired Macros) for Reuse........... 131
3.8.3 Designing in a Team-Based Environment.................................................... 132
3.8.4 Enabling Designers on a Team to Optimize Independently.............................134
3.8.5 Performing Design Iterations With Lower-Level Partitions..............................138

3.9 Creating a Design Floorplan With LogicLock Regions................................................ 139

3.9.1 Creating and Manipulating LogicLock Regions..............................................140
3.9.2 Changing Partition Placement with LogicLock Changes..................................141

3.10 Incremental Compilation Restrictions................................................................... 141

3.10.1 When Timing Performance May Not Be Preserved Exactly............................141
3.10.2 When Placement and Routing May Not Be Preserved Exactly........................142
3.10.3 Using Incremental Compilation With Intel Quartus Prime Archive Files.......... 142
3.10.4 Formal Verification Support.....................................................................142
3.10.5 Signal Probe Pins and Engineering Change Orders......................................143
3.10.6 Signal Tap Logic Analyzer in Exported Partitions.........................................143
3.10.7 External Logic Analyzer Interface in Exported Partitions.............................. 144
3.10.8 Assignments Made in HDL Source Code in Exported Partitions..................... 144
3.10.9 Design Partition Script Limitations............................................................144
3.10.10 Restrictions on IP Core Partitions........................................................... 146
3.10.11 Restrictions on Intel Arria 10 Transceiver................................................ 146
3.10.12 Register Packing and Partition Boundaries............................................... 147
3.10.13 I/O Register Packing............................................................................ 147

3.11 Scripting Support.............................................................................................. 148

3.11.1 Tcl Scripting and Command-Line Examples................................................148

3.12 Document Revision History................................................................................. 152

4 Design Planning for Partial Reconfiguration.................................................................154

4.1 Terminology....................................................................................................... 154

4.1.1 Determining Resources for Partial Reconfiguration....................................... 156

4.2 An Example of a Partial Reconfiguration Design....................................................... 157
4.3 Partial Reconfiguration Modes............................................................................... 157

4.3.1 SCRUB Mode.......................................................................................... 158
4.3.2 AND/OR Mode.........................................................................................159
4.3.3 Programming File Sizes for a Partial Reconfiguration Project..........................160

4.4 Partial Reconfiguration Design Flow....................................................................... 161

4.4.1  Design Partitions for Partial Reconfiguration............................................... 163
4.4.2 Incremental Compilation Partitions for Partial Reconfiguration....................... 163
4.4.3 Partial Reconfiguration Controller Instantiation in the Design.........................164
4.4.4 Wrapper Logic for PR Regions................................................................... 167

4.5 Freeze Logic for PR Regions.................................................................................. 169

4.5.1 Clocks and Other Global Signals for a PR Design..........................................171
4.5.2 Floorplan Assignments for PR Designs........................................................ 172

4.6 Implementation Details for Partial Reconfiguration................................................... 173

4.6.1 Interface with the PR Control Block through a PR Host................................. 173
4.6.2 Partial Reconfiguration Pins.......................................................................175
4.6.3 PR Control Signals Interface..................................................................... 176

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

4

4.6.4 Reconfiguring a PR Region........................................................................176
4.6.5 Partial Reconfiguration Cycle Waveform...................................................... 178

4.7 Example of a Partial Reconfiguration Design with an External Host............................. 180

4.7.1 Example of Using an External Host with Multiple Devices.............................. 181

4.8 Example Partial Reconfiguration with an Internal Host.............................................. 182
4.9 Partial Reconfiguration Project Management............................................................183

4.9.1 Create Reconfigurable Revisions................................................................ 183
4.9.2 Compiling Reconfigurable Revisions........................................................... 184
4.9.3 Timing Closure for a Partial Reconfiguration Project......................................184
4.9.4 PR Bitstream Compression and Encryption..................................................184

4.10 Programming Files for a Partial Reconfiguration Project...........................................185

4.10.1 Generating Required Programming Files................................................... 188
4.10.2 Generate PR Programming Files with the Convert Programming Files

Dialog Box............................................................................................ 188

4.11 On-Chip Debug for PR Designs............................................................................ 191
4.12 Partial Reconfiguration Known Limitations............................................................. 192

4.12.1 Memory Blocks Initialization Requirement for PR Designs............................ 192
4.12.2 M20K RAM Blocks in PR Designs.............................................................. 192
4.12.3 MLAB Blocks in PR designs......................................................................194
4.12.4 Implementing Memories with Initialized Content........................................ 195
4.12.5 Initializing M20K Blocks with a Double PR Cycle......................................... 197

4.13 Document Revision History................................................................................. 197

5 Creating a System with Platform Designer (Standard).................................................198

5.1 Interface Support in Platform Designer (Standard).................................................. 199
5.2 Introduction to the Platform Designer (Standard) IP Catalog..................................... 199

5.2.1  Installing and Licensing IP Cores.............................................................. 200
5.2.2 Adding IP Cores to IP Catalog................................................................... 200
5.2.3 General Settings for IP.............................................................................202
5.2.4 Set up the IP Index File (.ipx) to Search for IP Components ........................ 202
5.2.5 Integrate Third-Party IP Components into the Platform Designer (Standard)

IP Catalog............................................................................................. 203

5.3 Create a Platform Designer (Standard) System....................................................... 204

5.3.1 Start a New Project or Open a Recent Project in Platform Designer (Standard) 204
5.3.2 Specify the Target Device......................................................................... 204
5.3.3 Add IP Components (IP Cores) to a Platform Designer (Standard) System...... 205
5.3.4 Connect IP Components in Your Platform Designer (Standard) System........... 206
5.3.5 View Your Platform Designer (Standard) System..........................................208
5.3.6 Navigate Your Platform Designer (Standard) System.................................... 213
5.3.7 Specify IP Component Parameters............................................................. 214
5.3.8 Define Platform Designer (Standard) Instance Parameters............................ 217
5.3.9 Create a Custom IP Component (_hw.tcl)................................................... 226

5.4 Upgrade Outdated IP Components in Platform Designer (Standard)............................226

5.4.1 Troubleshooting IP or Platform Designer System Upgrade............................. 227

5.5 Create and Manage Hierarchical Platform Designer (Standard) Systems......................229

5.5.1 Add a Subsystem to Your Platform Designer (Standard) Design..................... 230
5.5.2 Drill into a Platform Designer (Standard) Subsystem to Explore its Contents... 230
5.5.3 Edit a Platform Designer (Standard) Subsystem.......................................... 232
5.5.4 Change the Hierarchy Level of a Platform Designer (Standard) Component..... 232
5.5.5 Save New Platform Designer (Standard) Subsystem.....................................233
5.5.6 Create an IP Component Based on a Platform Designer (Standard) System.....233

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

5

5.5.7 Hierarchical System Using Instance Parameters Example.............................. 233

5.6 View and Filter Clock and Reset Domains in Your Platform Designer (Standard) System 239

5.6.1 View Clock Domains in Your Platform Designer (Standard) System.................240
5.6.2 View Reset Domains in Your Platform Designer (Standard) System................ 241
5.6.3 Filter Platform Designer (Standard) Clock and Reset Domains in the

System Contents Tab.............................................................................. 242

5.6.4 View Avalon Memory Mapped Domains in Your Platform Designer

(Standard) System................................................................................. 243

5.7 Specify Platform Designer (Standard) Interconnect Requirements..............................245
5.8 Manage Platform Designer (Standard) System Security............................................ 247

5.8.1 Configure Platform Designer (Standard) Security Settings Between Interfaces.248
5.8.2 Specify a Default Slave in a Platform Designer (Standard) System................. 248
5.8.3 Access Undefined Memory Regions............................................................ 249

5.9 Integrate a Platform Designer (Standard) System with the Intel Quartus Prime

Software........................................................................................................ 250
5.9.1 Integrate a Platform Designer (Standard) System and the Intel Quartus

Prime Software With the .qsys File............................................................251

5.9.2 Integrate a Platform Designer (Standard) System and the Intel Quartus

Prime Software With the .qip File..............................................................251

5.10 Manage IP Settings in the Intel Quartus Prime Software......................................... 252

5.10.1 Opening Platform Designer (Standard) with Additional Memory....................253

5.11 Set Platform Designer (Standard) Clock Constraints............................................... 253
5.12 Generate a Platform Designer (Standard) System.................................................. 254

5.12.1 Set the Generation ID............................................................................ 255
5.12.2 Generate Files for Synthesis and Simulation.............................................. 255
5.12.3 Generate Files for a Testbench Platform Designer (Standard) System........... 257
5.12.4 Platform Designer (Standard) Simulation Scripts........................................261
5.12.5 Simulating Software Running on a Nios II Processor...................................263
5.12.6 Add Assertion Monitors for Simulation...................................................... 264
5.12.7 CMSIS Support for the HPS IP Component................................................ 265
5.12.8 Generate Header Files............................................................................265

5.13 Explore and Manage Platform Designer (Standard) Interconnect.............................. 266

5.13.1 Manually Controlling Pipelining in the Platform Designer (Standard)

Interconnect..........................................................................................267

5.14 Implement Performance Monitoring..................................................................... 269
5.15 Platform Designer (Standard) 64-Bit Addressing Support........................................ 269

5.15.1 Support for Avalon-MM Non-Power of Two Data Widths............................... 269

5.16 Platform Designer (Standard) System Example Designs..........................................270
5.17 Platform Designer (Standard) Command-Line Utilities............................................ 270

5.17.1 Run the Platform Designer (Standard) Editor with qsys-edit........................ 270
5.17.2 Scripting IP Core Generation................................................................... 271
5.17.3 Display Available IP Components with ip-catalog........................................273
5.17.4 Create an .ipx File with ip-make-ipx......................................................... 274
5.17.5 Generate Simulation Scripts....................................................................275
5.17.6 Generate a Platform Designer (Standard) System with qsys-script............... 275
5.17.7 Platform Designer (Standard) Scripting Command Reference.......................277
5.17.8 Platform Designer (Standard) Scripting Property Reference......................... 378

5.18 Document Revision History................................................................................. 406

6 Creating Platform Designer (Standard) Components................................................... 408

6.1 Platform Designer (Standard) Components............................................................. 408

6.1.1 Interface Support in Platform Designer (Standard).......................................408

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

6

6.1.2 Component Structure.............................................................................. 409
6.1.3 Component File Organization.................................................................... 410
6.1.4 Component Versions................................................................................410

6.2 Design Phases of an IP Component........................................................................411
6.3 Create IP Components in the Platform Designer (Standard) Component Editor............ 412

6.3.1 Save an IP Component and Create the _hw.tcl File...................................... 414
6.3.2 Edit an IP Component with the Platform Designer (Standard) Component

Editor................................................................................................... 415

6.4 Specify IP Component Type Information................................................................. 415
6.5 Create an HDL File in the Platform Designer (Standard) Component Editor..................417
6.6 Create an HDL File Using a Template in the Platform Designer (Standard)

Component Editor........................................................................................... 417

6.7 Specify Synthesis and Simulation Files in the Platform Designer (Standard)

Component Editor........................................................................................... 419
6.7.1 Specify HDL Files for Synthesis in the Platform Designer (Standard)

Component Editor.................................................................................. 420

6.7.2 Analyze Synthesis Files in the Platform Designer (Standard) Component Editor421
6.7.3 Name HDL Signals for Automatic Interface and Type Recognition in the

Platform Designer (Standard) Component Editor........................................ 422

6.7.4 Specify Files for Simulation in the Component Editor.................................... 423
6.7.5 Include an Internal Register Map Description in the .svd for Slave

Interfaces Connected to an HPS Component.............................................. 424

6.8 Add Signals and Interfaces in the Platform Designer (Standard) Component Editor...... 425
6.9 Specify Parameters in the Platform Designer (Standard) Component Editor................. 426

6.9.1 Valid Ranges for Parameters in the _hw.tcl File............................................429
6.9.2 Types of Platform Designer (Standard) Parameters...................................... 429
6.9.3 Declare Parameters with Custom _hw.tcl Commands....................................430
6.9.4 Validate Parameter Values with a Validation Callback....................................432

6.10 Declaring SystemVerilog Interfaces in _hw.tcl........................................................432
6.11 User Alterable HDL Parameters in _hw.tcl............................................................. 434
6.12 Control Interfaces Dynamically with an Elaboration Callback....................................436
6.13 Control File Generation Dynamically with Parameters and a Fileset Callback.............. 436
6.14 Create a Composed Component or Subsystem...................................................... 438
6.15  Create an IP Component with Platform Designer (Standard) a System View

Different from the Generated Synthesis Output Files............................................ 440

6.16 Add Component Instances to a Static or Generated Component............................... 441

6.16.1 Static Components................................................................................ 442
6.16.2 Generated Components..........................................................................443
6.16.3 Design Guidelines for Adding Component Instances................................... 446

6.17 Document Revision History................................................................................. 446

7 Platform Designer (Standard) Interconnect.................................................................448

7.1 Memory-Mapped Interfaces.................................................................................. 448

7.1.1 Platform Designer (Standard) Packet Format...............................................450
7.1.2 Interconnect Domains..............................................................................453
7.1.3 Master Network Interfaces........................................................................455
7.1.4 Slave Network Interfaces......................................................................... 458
7.1.5 Arbitration..............................................................................................460
7.1.6 Memory-Mapped Arbiter...........................................................................464
7.1.7 Datapath Multiplexing Logic...................................................................... 466
7.1.8 Width Adaptation.................................................................................... 466
7.1.9 Burst Adapter......................................................................................... 468

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

7

7.1.10 Read and Write Responses......................................................................470
7.1.11 Platform Designer (Standard) Address Decoding........................................ 471

7.2 Avalon Streaming Interfaces.................................................................................472

7.2.1 Avalon-ST Adapters................................................................................. 474

7.3 Interrupt Interfaces.............................................................................................482

7.3.1 Individual Requests IRQ Scheme............................................................... 482
7.3.2 Assigning IRQs in Platform Designer (Standard).......................................... 483

7.4 Clock Interfaces..................................................................................................485

7.4.1 (High Speed Serial Interface) HSSI Clock Interfaces.................................... 486

7.5 Reset Interfaces..................................................................................................491

7.5.1 Single Global Reset Signal Implemented by Platform Designer (Standard).......492
7.5.2 Reset Controller...................................................................................... 492
7.5.3 Reset Bridge...........................................................................................492
7.5.4 Reset Sequencer..................................................................................... 493

7.6 Conduits............................................................................................................ 504
7.7 Interconnect Pipelining........................................................................................ 504

7.7.1 Manually Controlling Pipelining in the Platform Designer (Standard)

Interconnect..........................................................................................506

7.8 Error Correction Coding (ECC) in Platform Designer (Standard) Interconnect...............507
7.9 AMBA 3 AXI Protocol Specification Support (version 1.0).......................................... 507

7.9.1 Channels................................................................................................508
7.9.2 Cache Support........................................................................................ 508
7.9.3 Security Support..................................................................................... 509
7.9.4 Atomic Accesses..................................................................................... 509
7.9.5 Response Signaling................................................................................. 509
7.9.6 Ordering Model....................................................................................... 509
7.9.7 Data Buses.............................................................................................510
7.9.8 Unaligned Address Commands.................................................................. 510
7.9.9 Avalon and AXI Transaction Support.......................................................... 510

7.10 AMBA 3 APB Protocol Specification Support (version 1.0)........................................ 511

7.10.1 Bridges................................................................................................ 511
7.10.2 Burst Adaptation................................................................................... 512
7.10.3 Width Adaptation...................................................................................512
7.10.4 Error Response..................................................................................... 512

7.11 AMBA 4 AXI Memory-Mapped Interface Support (version 2.0)..................................512

7.11.1 Burst Support....................................................................................... 512
7.11.2 QoS.....................................................................................................512
7.11.3 Regions................................................................................................513
7.11.4 Write Response Dependency................................................................... 513
7.11.5 AWCACHE and ARCACHE........................................................................ 513
7.11.6 Width Adaptation and Data Packing in Platform Designer (Standard)............ 513
7.11.7 Ordering Model..................................................................................... 513
7.11.8 Read and Write Allocate......................................................................... 514
7.11.9 Locked Transactions...............................................................................514
7.11.10 Memory Types.....................................................................................514
7.11.11 Mismatched Attributes..........................................................................514
7.11.12 Signals...............................................................................................514

7.12 AMBA 4 AXI Streaming Interface Support (version 1.0).......................................... 514

7.12.1 Connection Points..................................................................................515
7.12.2 Adaptation............................................................................................515

7.13 AMBA 4 AXI-Lite Protocol Specification Support (version 2.0).................................. 516

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

8

7.13.1 AMBA 4 AXI-Lite Signals.........................................................................516
7.13.2 AMBA 4 AXI-Lite Bus Width.....................................................................516
7.13.3 AMBA 4 AXI-Lite Outstanding Transactions................................................516
7.13.4 AMBA 4 AXI-Lite IDs.............................................................................. 516
7.13.5 Connections Between AMBA 3 AXI,AMBA 4 AXI and AMBA 4 AXI-Lite............ 517
7.13.6 AMBA 4 AXI-Lite Response Merging..........................................................517

7.14 Port Roles (Interface Signal Types)...................................................................... 517

7.14.1 AXI Master Interface Signal Types............................................................517
7.14.2 AXI Slave Interface Signal Types............................................................. 519
7.14.3 AMBA 4 AXI Master Interface Signal Types................................................ 520
7.14.4 AMBA 4 AXI Slave Interface Signal Types..................................................521
7.14.5 AMBA 4 AXI-Stream Master and Slave Interface Signal Types...................... 523
7.14.6 APB Interface Signal Types..................................................................... 523
7.14.7 Avalon Memory-Mapped Interface Signal Roles.......................................... 523
7.14.8 Avalon Streaming Interface Signal Roles ..................................................527
7.14.9 Avalon Clock Source Signal Roles ............................................................528
7.14.10 Avalon Clock Sink Signal Roles ............................................................. 528
7.14.11 Avalon Conduit Signal Roles ................................................................. 528
7.14.12 Avalon Tristate Conduit Signal Roles ...................................................... 528
7.14.13 Avalon Tri-State Slave Interface Signal Types.......................................... 530
7.14.14 Avalon Interrupt Sender Signal Roles .....................................................531
7.14.15 Avalon Interrupt Receiver Signal Roles ...................................................531

7.15 Document Revision History................................................................................. 531

8 Optimizing Platform Designer (Standard) System Performance...................................533

8.1 Designing with Avalon and AXI Interfaces...............................................................533

8.1.1 Designing Streaming Components............................................................. 534
8.1.2 Designing Memory-Mapped Components.................................................... 534

8.2 Using Hierarchy in Systems.................................................................................. 535
8.3 Using Concurrency in Memory-Mapped Systems...................................................... 538

8.3.1 Implementing Concurrency With Multiple Masters........................................ 539
8.3.2 Implementing Concurrency With Multiple Slaves..........................................540
8.3.3 Implementing Concurrency with DMA Engines............................................. 542

8.4 Inserting Pipeline Stages to Increase System Frequency ..........................................543
8.5 Using Bridges..................................................................................................... 543

8.5.1 Using Bridges to Increase System Frequency.............................................. 544
8.5.2 Using Bridges to Minimize Design Logic...................................................... 547
8.5.3 Using Bridges to Minimize Adapter Logic.....................................................549
8.5.4 Considering the Effects of Using Bridges.....................................................550

8.6 Increasing Transfer Throughput.............................................................................556

8.6.1 Using Pipelined Transfers..........................................................................557
8.6.2 Arbitration Shares and Bursts................................................................... 558

8.7 Reducing Logic Utilization.....................................................................................562

8.7.1 Minimizing Interconnect Logic to Reduce Logic Unitization.............................562
8.7.2 Minimizing Arbitration Logic by Consolidating Multiple Interfaces................... 563
8.7.3 Reducing Logic Utilization With Multiple Clock Domains.................................565
8.7.4 Duration of Transfers Crossing Clock Domains ............................................ 567

8.8 Reducing Power Consumption............................................................................... 568

8.8.1 Reducing Power Consumption With Multiple Clock Domains........................... 568
8.8.2 Reducing Power Consumption by Minimizing Toggle Rates............................. 570
8.8.3 Reducing Power Consumption by Disabling Logic......................................... 572

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

9

8.9 Reset Polarity and Synchronization in Platform Designer (Standard)........................... 573
8.10 Optimizing Platform Designer (Standard) System Performance Design Examples........576

8.10.1 Avalon Pipelined Read Master Example..................................................... 576
8.10.2 Multiplexer Examples............................................................................. 578

8.11 Document Revision History................................................................................. 579

9 Component Interface Tcl Reference............................................................................. 581

9.1 Platform Designer (Standard) _hw.tcl Command Reference.......................................581

9.1.1 Interfaces and Ports................................................................................ 582
9.1.2 Parameters.............................................................................................600
9.1.3 Display Items......................................................................................... 611
9.1.4 Module Definition.................................................................................... 618
9.1.5 Composition........................................................................................... 630
9.1.6 Fileset Generation................................................................................... 650
9.1.7 Miscellaneous......................................................................................... 661
9.1.8 SystemVerilog Interface Commands...........................................................667

9.2 Platform Designer (Standard) _hw.tcl Property Reference......................................... 673

9.2.1 Script Language Properties....................................................................... 674
9.2.2 Interface Properties.................................................................................675
9.2.3 SystemVerilog Interface Properties............................................................ 675
9.2.4 Instance Properties................................................................................. 676
9.2.5 Parameter Properties............................................................................... 677
9.2.6 Parameter Type Properties........................................................................679
9.2.7 Parameter Status Properties..................................................................... 680
9.2.8 Port Properties........................................................................................681
9.2.9 Direction Properties................................................................................. 683
9.2.10 Display Item Properties.......................................................................... 684
9.2.11 Display Item Kind Properties................................................................... 685
9.2.12 Display Hint Properties........................................................................... 686
9.2.13 Module Properties..................................................................................687
9.2.14 Fileset Properties...................................................................................689
9.2.15 Fileset Kind Properties............................................................................690
9.2.16 Callback Properties................................................................................ 691
9.2.17 File Attribute Properties..........................................................................692
9.2.18 File Kind Properties................................................................................693
9.2.19 File Source Properties............................................................................ 694
9.2.20 Simulator Properties.............................................................................. 695
9.2.21 Port VHDL Type Properties...................................................................... 696
9.2.22 System Info Type Properties................................................................... 697
9.2.23 Design Environment Type Properties........................................................ 699
9.2.24 Units Properties.....................................................................................700
9.2.25 Operating System Properties...................................................................701
9.2.26 Quartus.ini Type Properties..................................................................... 702

9.3 Document Revision History...................................................................................703

10 Platform Designer (Standard) System Design Components........................................704

10.1 Bridges............................................................................................................ 704

10.1.1 Clock Bridge......................................................................................... 705
10.1.2 Avalon-MM Clock Crossing Bridge............................................................ 706
10.1.3 Avalon-MM Pipeline Bridge...................................................................... 708
10.1.4 Avalon-MM Unaligned Burst Expansion Bridge............................................709

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

10

10.1.5 Bridges Between Avalon and AXI Interfaces.............................................. 712
10.1.6 AXI Bridge............................................................................................713
10.1.7 AXI Timeout Bridge............................................................................... 718
10.1.8 Address Span Extender.......................................................................... 722

10.2 Error Response Slave......................................................................................... 727

10.2.1 Error Response Slave Parameters............................................................ 728
10.2.2 Error Response Slave CSR Registers.........................................................729
10.2.3 Designating a Default Slave in the System Contents Tab............................. 732

10.3 Tri-State Components........................................................................................ 733

10.3.1 Generic Tri-State Controller.....................................................................735
10.3.2 Tri-State Conduit Pin Sharer....................................................................735
10.3.3 Tri-State Conduit Bridge......................................................................... 736

10.4 Test Pattern Generator and Checker Cores............................................................ 736

10.4.1 Test Pattern Generator........................................................................... 737
10.4.2 Test Pattern Checker.............................................................................. 739
10.4.3 Software Programming Model for the Test Pattern Generator and Checker

Cores................................................................................................... 740

10.4.4 Test Pattern Generator API......................................................................744
10.4.5 Test Pattern Checker API........................................................................ 749

10.5 Avalon-ST Splitter Core...................................................................................... 756

10.5.1 Splitter Core Backpressure......................................................................756
10.5.2 Splitter Core Interfaces.......................................................................... 757
10.5.3 Splitter Core Parameters........................................................................ 757

10.6 Avalon-ST Delay Core........................................................................................ 758

10.6.1 Delay Core Reset Signal......................................................................... 758
10.6.2 Delay Core Interfaces............................................................................ 758
10.6.3 Delay Core Parameters...........................................................................759

10.7 Avalon-ST Round Robin Scheduler....................................................................... 760

10.7.1 Almost-Full Status Interface (Round Robin Scheduler)................................ 760
10.7.2 Request Interface (Round Robin Scheduler).............................................. 760
10.7.3 Round Robin Scheduler Operation............................................................ 760
10.7.4 Round Robin Scheduler Parameters..........................................................761

10.8 Avalon Packets to Transactions Converter............................................................. 762

10.8.1 Packets to Transactions Converter Interfaces.............................................762
10.8.2 Packets to Transactions Converter Operation............................................. 762

10.9 Avalon-ST Streaming Pipeline Stage.....................................................................764
10.10 Streaming Channel Multiplexer and Demultiplexer Cores....................................... 765

10.10.1 Software Programming Model For the Multiplexer and Demultiplexer

Components.......................................................................................... 766

10.10.2 Avalon-ST Multiplexer...........................................................................766
10.10.3 Avalon-ST Demultiplexer...................................................................... 768

10.11 Single-Clock and Dual-Clock FIFO Cores............................................................. 769

10.11.1 Interfaces Implemented in FIFO Cores....................................................770
10.11.2 FIFO Operating Modes.......................................................................... 771
10.11.3 Fill Level of the FIFO Buffer................................................................... 772
10.11.4 Almost-Full and Almost-Empty Thresholds to Prevent Overflow and

Underflow............................................................................................. 772

10.11.5 Single-Clock and Dual-Clock FIFO Core Parameters.................................. 772
10.11.6 Avalon-ST Single-Clock FIFO Registers....................................................773

10.12 Document Revision History............................................................................... 774

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

11

11 Recommended Design Practices.................................................................................776

11.1 Following Synchronous FPGA Design Practices....................................................... 776

11.1.1 Implementing Synchronous Designs.........................................................776
11.1.2 Asynchronous Design Hazards.................................................................777

11.2 HDL Design Guidelines....................................................................................... 778

11.2.1 Optimizing Combinational Logic............................................................... 778
11.2.2 Optimizing Clocking Schemes..................................................................781
11.2.3 Optimizing Physical Implementation and Timing Closure............................. 786
11.2.4 Optimizing Power Consumption............................................................... 789
11.2.5 Managing Design Metastability................................................................ 789

11.3 Checking Design Violations................................................................................. 789

11.3.1 Validating Against Design Rules............................................................... 789
11.3.2 Creating Custom Design Rules.................................................................792

11.4 Use Clock and Register-Control Architectural Features............................................ 796

11.4.1 Use Global Reset Resources.................................................................... 796
11.4.2 Use Global Clock Network Resources........................................................ 805
11.4.3 Use Clock Region Assignments to Optimize Clock Constraints...................... 806
11.4.4 Avoid Asynchronous Register Control Signals.............................................807

11.5 Implementing Embedded RAM.............................................................................807
11.6 Document Revision History................................................................................. 808

12 Recommended HDL Coding Styles ............................................................................. 810

12.1 Using Provided HDL Templates............................................................................ 810

12.1.1 Inserting HDL Code from a Provided Template........................................... 810

12.2 Instantiating IP Cores in HDL.............................................................................. 811
12.3 Inferring Multipliers and DSP Functions................................................................ 812

12.3.1 Inferring Multipliers............................................................................... 812
12.3.2 Inferring Multiply-Accumulator and Multiply-Adder Functions....................... 813

12.4 Inferring Memory Functions from HDL Code ......................................................... 816

12.4.1 Inferring RAM functions from HDL Code....................................................817
12.4.2 Inferring ROM Functions from HDL Code................................................... 834
12.4.3 Inferring Shift Registers in HDL Code....................................................... 836

12.5 Register and Latch Coding Guidelines................................................................... 839

12.5.1 Register Power-Up Values....................................................................... 840
12.5.2 Secondary Register Control Signals Such as Clear and Clock Enable............. 841
12.5.3 Latches ............................................................................................... 844

12.6 General Coding Guidelines.................................................................................. 847

12.6.1 Tri-State Signals ...................................................................................847
12.6.2 Clock Multiplexing..................................................................................848
12.6.3 Adder Trees ......................................................................................... 850
12.6.4 State Machine HDL Guidelines................................................................. 852
12.6.5 Multiplexer HDL Guidelines .................................................................... 858
12.6.6 Cyclic Redundancy Check Functions ........................................................ 861
12.6.7 Comparator HDL Guidelines.................................................................... 863
12.6.8 Counter HDL Guidelines..........................................................................864

12.7 Designing with Low-Level Primitives.....................................................................864
12.8 Document Revision History ................................................................................ 865

13 Managing Metastability with the Intel Quartus Prime Software................................. 867

13.1 Metastability Analysis in the Intel Quartus Prime Software...................................... 868

13.1.1 Synchronization Register Chains.............................................................. 868

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

12

13.1.2 Identify Synchronizers for Metastability Analysis........................................ 869
13.1.3 How Timing Constraints Affect Synchronizer Identification and

Metastability Analysis..............................................................................869

13.2 Metastability and MTBF Reporting........................................................................ 870

13.2.1 Metastability Reports............................................................................. 871
13.2.2 Synchronizer Data Toggle Rate in MTBF Calculation.................................... 873

13.3 MTBF Optimization............................................................................................ 873

13.3.1 Synchronization Register Chain Length..................................................... 874

13.4 Reducing Metastability Effects............................................................................. 875

13.4.1 Apply Complete System-Centric Timing Constraints for the Timing Analyzer.. 875
13.4.2 Force the Identification of Synchronization Registers.................................. 875
13.4.3 Set the Synchronizer Data Toggle Rate..................................................... 876
13.4.4 Optimize Metastability During Fitting........................................................ 876
13.4.5 Increase the Length of Synchronizers to Protect and Optimize..................... 876
13.4.6 Set Fitter Effort to Standard Fit instead of Auto Fit..................................... 876
13.4.7 Increase the Number of Stages Used in Synchronizers................................877
13.4.8 Select a Faster Speed Grade Device......................................................... 877

13.5 Scripting Support.............................................................................................. 877

13.5.1 Identifying Synchronizers for Metastability Analysis....................................878
13.5.2 Synchronizer Data Toggle Rate in MTBF Calculation.................................... 878
13.5.3 report_metastability and Tcl Command.....................................................878
13.5.4 MTBF Optimization.................................................................................879
13.5.5 Synchronization Register Chain Length..................................................... 879

13.6 Managing Metastability.......................................................................................879
13.7 Document Revision History................................................................................. 879

14 Best Practices for Incremental Compilation Partitions and Floorplan Assignments.... 881

14.1 About Incremental Compilation and Floorplan Assignments..................................... 881
14.2 Incremental Compilation Overview.......................................................................881

14.2.1 Recommendations for the Netlist Type......................................................882

14.3 Design Flows Using Incremental Compilation.........................................................883

14.3.1 Using Standard Flow.............................................................................. 883
14.3.2  Using Team-Based Flow.........................................................................883
14.3.3  Combining Design Flows........................................................................883
14.3.4 Project Management in Team-Based Design Flows......................................884

14.4 Why Plan Partitions and Floorplan Assignments?.................................................... 885

14.4.1 Partition Boundaries and Optimization...................................................... 885

14.5 Guidelines for Incremental Compilation................................................................ 888

14.5.1 General Partitioning Guidelines................................................................888
14.5.2 Design Partition Guidelines..................................................................... 890
14.5.3 Consider a Cascaded Reset Structure....................................................... 902
14.5.4 Design Partition Guidelines for Third-Party IP Delivery................................ 903

14.6 Checking Partition Quality...................................................................................908

14.6.1 Incremental Compilation Advisor............................................................. 908
14.6.2 Design Partition Planner......................................................................... 908
14.6.3 Viewing Design Partition Planner and Floorplan Side-by-Side....................... 910
14.6.4 Partition Statistics Report....................................................................... 911
14.6.5 Report Partition Timing in the Timing Analyzer...........................................911
14.6.6 Check if Partition Assignments Impact the Quality of Results....................... 912

14.7 

Including 

SDC 

Constraints 

from 

Lower-Level 

Partitions 

for

Third-Party IP Delivery..................................................................................... 912

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

13

14.7.1 Creating an .sdc File with Project-Wide Constraints.................................... 913
14.7.2 Creating an .sdc with Partition-Specific Constraints.................................... 915
14.7.3 Consolidating the .sdc in the Top-Level Design...........................................916

14.8 Introduction to Design Floorplans........................................................................ 916

14.8.1 The Difference between Logical Partitions and Physical Regions....................917
14.8.2 Why Create a Floorplan?.........................................................................917
14.8.3 When to Create a Floorplan.....................................................................919

14.9 Design Floorplan Placement Guidelines.................................................................919

14.9.1 Flow for Creating a Floorplan...................................................................920
14.9.2 Assigning Partitions to LogicLock Regions..................................................920
14.9.3 How to Size and Place Regions................................................................ 921
14.9.4 Modifying Region Size and Origin............................................................. 921
14.9.5 I/O Connections.................................................................................... 922
14.9.6 LogicLock Resource Exclusions................................................................ 922
14.9.7 Creating Non-Rectangular Regions........................................................... 924

14.10 Checking Floorplan Quality................................................................................925

14.10.1 Incremental Compilation Advisor........................................................... 925
14.10.2 LogicLock Region Resource Estimates..................................................... 925
14.10.3 LogicLock Region Properties Statistics Report...........................................925
14.10.4 Locate the Intel Quartus Prime Timing Analyzer Path in the Chip Planner.....925
14.10.5 Inter-Region Connection Bundles........................................................... 925
14.10.6 Routing Utilization................................................................................926
14.10.7 Ensure Floorplan Assignments Do Not Significantly Impact Quality of

Results................................................................................................. 926

14.11 Recommended Design Flows and Application Examples......................................... 926

14.11.1 Create a Floorplan for Major Design Blocks..............................................926
14.11.2 Create a Floorplan Assignment for One Design Block with Difficult Timing....927
14.11.3 Create a Floorplan as the Project Lead in a Team-Based Flow.....................928

14.12 Document Revision History............................................................................... 928

15 Mitigating Single Event Upset.................................................................................... 930

15.1 Understanding Failure Rates................................................................................931
15.2 Mitigating SEU Effects in Embedded User RAM.......................................................931

15.2.1 Configuring RAM to Enable ECC............................................................... 932

15.3 Mitigating SEU Effects in Configuration RAM ......................................................... 932
15.4 Internal Scrubbing.............................................................................................933
15.5 Recovering from SEU......................................................................................... 934
15.6 Planning for SEU Recovery..................................................................................934
15.7 Designating the Sensitivity of the Design Hierarchy ...............................................935

15.7.1 Hierarchy Tagging .................................................................................936
15.7.2 Using Partitions to Specify Logic Sensitivity ID ..........................................936
15.7.3 Advanced SEU Detection IP Core............................................................. 937

15.8 Understanding the Intel Quartus Prime SEU FIT Reports......................................... 938

15.8.1 Component FIT Rates.............................................................................939
15.8.2 Raw FIT............................................................................................... 939
15.8.3 Utilized FIT........................................................................................... 940
15.8.4 Mitigated FIT........................................................................................ 941
15.8.5 Architectural Vulnerability Factor............................................................. 942
15.8.6 Enabling the Projected SEU FIT by Component Usage Report.......................942

15.9 Triple-Module Redundancy.................................................................................. 942
15.10 Evaluating Your System's Response to Functional Upsets.......................................943

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

14

15.11 CRAM Error Detection Settings Reference............................................................943
15.12 Document Revision History............................................................................... 944

16 Intel Quartus Prime Integrated Synthesis..................................................................945

16.1 Design Flow......................................................................................................945

16.1.1 Intel Quartus Prime Integrated Synthesis Design and Compilation Flow.........947

16.2 Language Support............................................................................................. 948

16.2.1 Verilog and SystemVerilog Synthesis Support............................................ 948
16.2.2 VHDL Synthesis Support.........................................................................953
16.2.3 AHDL Support....................................................................................... 955
16.2.4 Schematic Design Entry Support..............................................................955
16.2.5 State Machine Editor..............................................................................955
16.2.6 Design Libraries.................................................................................... 955
16.2.7 Using Parameters/Generics..................................................................... 958

16.3 Incremental Compilation.................................................................................... 963

16.3.1 Partitions for Preserving Hierarchical Boundaries........................................963
16.3.2 Parallel Synthesis.................................................................................. 964
16.3.3 Intel Quartus Prime Exported Partition File as Source................................. 964

16.4 Intel Quartus Prime Synthesis Options................................................................. 965

16.4.1 Setting Synthesis Options.......................................................................965
16.4.2 Optimization Technique.......................................................................... 969
16.4.3 Auto Gated Clock Conversion.................................................................. 969
16.4.4 Enabling Timing-Driven Synthesis............................................................971
16.4.5 SDC Constraint Protection.......................................................................971
16.4.6 PowerPlay Power Optimization.................................................................971
16.4.7 Limiting Resource Usage in Partitions....................................................... 971
16.4.8 Restructure Multiplexers......................................................................... 973
16.4.9 Synthesis Effort.....................................................................................974
16.4.10 Fitter Intial Placement Seed.................................................................. 974
16.4.11 State Machine Processing......................................................................974
16.4.12 Safe State Machine.............................................................................. 978
16.4.13 Power-Up Level................................................................................... 979
16.4.14 Power-Up Don’t Care............................................................................980
16.4.15 Remove Duplicate Registers.................................................................. 981
16.4.16 Preserve Registers............................................................................... 981
16.4.17 Disable Register Merging/Don’t Merge Register........................................ 982
16.4.18 Noprune Synthesis Attribute/Preserve Fan-out Free Register Node..............983
16.4.19 Keep Combinational Node/Implement as Output of Logic Cell.....................984
16.4.20 Disabling Synthesis Netlist Optimizations with dont_retime Attribute.......... 985
16.4.21 Disabling Synthesis Netlist Optimizations with dont_replicate Attribute........985
16.4.22 Maximum Fan-Out............................................................................... 986
16.4.23 Controlling Clock Enable Signals with Auto Clock Enable Replacement

and direct_enable...................................................................................987

16.5 Inferring Multiplier, DSP, and Memory Functions from HDL Code...............................988

16.5.1 Multiply-Accumulators and Multiply-Adders............................................... 988
16.5.2 Shift Registers...................................................................................... 989
16.5.3 RAM and ROM....................................................................................... 989
16.5.4 Resource Aware RAM, ROM, and Shift-Register Inference............................ 990
16.5.5 Auto RAM to Logic Cell Conversion........................................................... 991
16.5.6 RAM Style and ROM Style—for Inferred Memory........................................ 991
16.5.7 RAM Style Attribute—For Shift Registers Inference..................................... 993

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

15

16.5.8 Disabling Add Pass-Through Logic to Inferred RAMs no_rw_check Attribute... 994
16.5.9 RAM Initialization File—for Inferred Memory.............................................. 996
16.5.10 Multiplier Style—for Inferred Multipliers.................................................. 997
16.5.11 Full Case Attribute............................................................................... 999
16.5.12 Parallel Case..................................................................................... 1000
16.5.13 Translate Off and On / Synthesis Off and On.......................................... 1001
16.5.14 Ignore translate_off and synthesis_off Directives....................................1002
16.5.15 Read Comments as HDL......................................................................1002
16.5.16 Use I/O Flipflops................................................................................ 1003
16.5.17 Specifying Pin Locations with chip_pin.................................................. 1004
16.5.18 Using altera_attribute to Set Intel Quartus Prime Logic Options................1006

16.6 Analyzing Synthesis Results.............................................................................. 1008

16.6.1 Analysis & Synthesis Section of the Compilation Report.............................1008
16.6.2 Project Navigator.................................................................................1009

16.7 Analyzing and Controlling Synthesis Messages.....................................................1009

16.7.1 Intel Quartus Prime Messages............................................................... 1009
16.7.2 VHDL and Verilog HDL Messages............................................................1010

16.8 Node-Naming Conventions in Intel Quartus Prime Integrated Synthesis.................. 1012

16.8.1 Hierarchical Node-Naming Conventions...................................................1013
16.8.2 Node-Naming Conventions for Registers (DFF or D Flipflop Atoms)............. 1013
16.8.3 Register Changes During Synthesis........................................................ 1014
16.8.4 Preserving Register Names....................................................................1016
16.8.5 Node-Naming Conventions for Combinational Logic Cells........................... 1016
16.8.6 Preserving Combinational Logic Names................................................... 1018

16.9 Scripting Support............................................................................................ 1018

16.9.1 Adding an HDL File to a Project and Setting the HDL Version..................... 1019
16.9.2 Assigning a Pin....................................................................................1020
16.9.3 Creating Design Partitions for Incremental Compilation............................. 1021
16.9.4 Intel Quartus Prime Synthesis Options....................................................1021

16.10 Document Revision History..............................................................................1021

17 Optimizing the Design Netlist...................................................................................1024

17.1 When to Use the Netlist Viewers: Analyzing Design Problems ................................1024
17.2 Intel Quartus Prime Design Flow with the Netlist Viewers...................................... 1025
17.3 RTL Viewer Overview....................................................................................... 1026
17.4 State Machine Viewer Overview......................................................................... 1028
17.5 Technology Map Viewer Overview.......................................................................1028
17.6 Introduction to the User Interface......................................................................1029

17.6.1 Netlist Navigator Pane.......................................................................... 1031
17.6.2 Properties Pane................................................................................... 1032
17.6.3 Netlist Viewers Find Pane......................................................................1033

17.7 Schematic View...............................................................................................1033

17.7.1 Display Schematics in Multiple Tabbed View.............................................1033
17.7.2 Schematic Symbols..............................................................................1034
17.7.3 Select Items in the Schematic View........................................................1037
17.7.4 Shortcut Menu Commands in the Schematic View.................................... 1038
17.7.5 Filtering in the Schematic View.............................................................. 1038
17.7.6 View Contents of Nodes in the Schematic View........................................ 1039
17.7.7 Moving Nodes in the Schematic View......................................................1040
17.7.8 View LUT Representations in the Technology Map Viewer...........................1041
17.7.9 Zoom Controls.....................................................................................1041

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

16

17.7.10 Navigating with the Bird's Eye View...................................................... 1042
17.7.11 Partition the Schematic into Pages........................................................1042
17.7.12 Follow Nets Across Schematic Pages..................................................... 1043

17.8 State Machine Viewer.......................................................................................1043

17.8.1 State Diagram View............................................................................. 1044
17.8.2 State Transition Table........................................................................... 1044
17.8.3 State Encoding Table............................................................................1044
17.8.4 Switch Between State Machines.............................................................1045

17.9 Cross-Probing to a Source Design File and Other Intel Quartus Prime Windows........ 1045
17.10 Cross-Probing to the Netlist Viewers from Other Intel Quartus Prime Windows....... 1046
17.11 Viewing a Timing Path.................................................................................... 1046
17.12 Document Revision History..............................................................................1047

18 Synopsys Synplify Support....................................................................................... 1049

18.1 About Synplify Support.....................................................................................1049
18.2 Design Flow.................................................................................................... 1049
18.3 Hardware Description Language Support.............................................................1051
18.4 Intel Device Family Support.............................................................................. 1051
18.5 Tool Setup...................................................................................................... 1051

18.5.1 Specifying the Intel Quartus Prime Software Version.................................1051
18.5.2 Exporting Designs to the Intel Quartus Prime Software Using NativeLink

Integration.......................................................................................... 1052

18.6 Synplify Software Generated Files...................................................................... 1053
18.7 Design Constraints Support...............................................................................1054

18.7.1 Running the Intel Quartus Prime Software Manually With the

Synplify-Generated Tcl Script................................................................. 1055

18.7.2 Passing Timing Analyzer SDC Timing Constraints to the Intel Quartus

Prime Software.................................................................................... 1055

18.8 Simulation and Formal Verification..................................................................... 1056
18.9 Synplify Optimization Strategies........................................................................ 1056

18.9.1 Using Synplify Premier to Optimize Your Design....................................... 1057
18.9.2 Using Implementations in Synplify Pro or Premier.................................... 1057
18.9.3 Timing-Driven Synthesis Settings...........................................................1057
18.9.4 FSM Compiler......................................................................................1059
18.9.5 Optimization Attributes and Options....................................................... 1060
18.9.6 Intel-Specific Attributes........................................................................ 1063

18.10 Guidelines for Intel FPGA IP Cores and Architecture-Specific Features................... 1063

18.10.1 Instantiating Intel FPGA IP Cores with the IP Catalog.............................. 1064
18.10.2 Including Files for Intel Quartus Prime Placement and Routing Only.......... 1068
18.10.3 Inferring Intel FPGA IP Cores from HDL Code.........................................1068

18.11 Incremental Compilation and Block-Based Design...............................................1073

18.11.1 Design Flow for Incremental Compilation...............................................1074
18.11.2 Creating a Design with Separate Netlist Files for Incremental Compilation..1075
18.11.3 Using MultiPoint Synthesis with Incremental Compilation.........................1075
18.11.4 Creating Multiple .vqm Files for a Incremental Compilation Flow With

Separate Synplify Projects..................................................................... 1079

18.11.5 Performing Incremental Compilation in the Intel Quartus Prime Software...1084

18.12 Document Revision History..............................................................................1084

19 Mentor Graphics Precision Synthesis Support.......................................................... 1086

19.1 About Precision RTL Synthesis Support............................................................... 1086
19.2 Design Flow.................................................................................................... 1086

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

17

19.2.1 Timing Optimization............................................................................. 1088

19.3 Intel Device Family Support.............................................................................. 1088
19.4 Precision Synthesis Generated Files....................................................................1088
19.5 Creating and Compiling a Project in the Precision Synthesis Software..................... 1089
19.6 Mapping the Precision Synthesis Design..............................................................1089

19.6.1 Setting Timing Constraints.................................................................... 1090
19.6.2 Setting Mapping Constraints..................................................................1090
19.6.3 Assigning Pin Numbers and I/O Settings................................................. 1090
19.6.4 Assigning I/O Registers........................................................................ 1091
19.6.5 Disabling I/O Pad Insertion................................................................... 1091
19.6.6 Controlling Fan-Out on Data Nets...........................................................1092

19.7 Synthesizing the Design and Evaluating the Results..............................................1092

19.7.1 Obtaining Accurate Logic Utilization and Timing Analysis Reports................1093

19.8 Exporting Designs to the Intel Quartus Prime Software Using NativeLink Integration.1093

19.8.1 Running the Intel Quartus Prime Software from within the Precision

Synthesis Software............................................................................... 1093

19.8.2 Running the Intel Quartus Prime Software Manually Using the Precision

Synthesis-Generated Tcl Script............................................................... 1094

19.8.3 Using the Intel Quartus Prime Software to Run the Precision Synthesis

Software............................................................................................. 1095

19.8.4 Passing Constraints to the Intel Quartus Prime Software........................... 1095

19.9 Guidelines for Intel FPGA IP Cores and Architecture-Specific Features..................... 1098

19.9.1 Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files............ 1099
19.9.2 Instantiating IP Cores With IP Catalog-Generated VHDL Files.....................1099
19.9.3 Instantiating Intellectual Property With the IP Catalog and Parameter Editor1099
19.9.4 Instantiating Black Box IP Functions With Generated Verilog HDL Files........ 1100
19.9.5 Instantiating Black Box IP Functions With Generated VHDL Files.................1100
19.9.6 Inferring Intel FPGA IP Cores from HDL Code...........................................1101

19.10 Incremental Compilation and Block-Based Design...............................................1106

19.10.1 Creating a Design with Precision RTL Plus Incremental Synthesis.............. 1106
19.10.2 Creating Multiple Mapped Netlist Files With Separate Precision Projects

or Implementations.............................................................................. 1108

19.10.3 Creating Black Boxes to Create Netlists.................................................1108
19.10.4 Creating Intel Quartus Prime Projects for Multiple Netlist Files..................1111
19.10.5 Hierarchy and Design Considerations.................................................... 1112

19.11 Document Revision History..............................................................................1112

Contents

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

18

1 Managing Intel

®

 Quartus

®

 Prime Projects

The Intel

®

 Quartus

®

 Prime software organizes and manages the elements of your

design within a project.

Click File > New Project Wizard to quickly setup and create a new design project.

Figure 1.

New Project Wizard

When you open a project, a unified GUI displays integrated project information. The

project encapsulates information about your design hierarchy, libraries, constraints,

and project settings.

You can save multiple revisions of your project to experiment with settings that

achieve your design goals. Intel Quartus Prime projects support team-based,

distributed work flows and a scripting interface.

QPS5V1 | 2017.10.06

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus

and  Stratix  words  and  logos  are  trademarks  of  Intel  Corporation  or  its  subsidiaries  in  the  U.S.  and/or  other

countries.  Intel  warrants  performance  of  its  FPGA  and  semiconductor  products  to  current  specifications  in

accordance with Intel's standard warranty, but reserves the right to make changes to any products and services

at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any

information,  product,  or  service  described  herein  except  as  expressly  agreed  to  in  writing  by  Intel.  Intel

customers  are  advised  to  obtain  the  latest  version  of  device  specifications  before  relying  on  any  published

information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2008

Registered

1.1 Understanding Intel Quartus Prime Projects

The Intel Quartus Prime software organizes your FPGA design work within a project. A
singleIntel Quartus PrimeProject File (

.qpf

) represents each design project. The text-

based .qpf references the Intel Quartus Prime Settings File (

.qsf

). The 

.qsf

references the project's design, constraint, and IP files, and stores and project-wide or

entity-specific settings that you specify in the GUI. The Intel Quartus Prime organizes

and maintains these various project files.

Table 1.

Intel Quartus Prime Project Files

File Type

Contains

To Edit

Format

Project file

Project and revision name

File 

➤

 New Project

Wizard

Intel Quartus Prime Project File (

.qpf

)

Project settings

Lists design files, entity

settings, target device,

synthesis directives,

placement constraints

Assignments 

➤

 Settings

Intel Quartus Prime Settings File (

.qsf

)

Project database

Compilation results

Project 

➤

 Export

Database

Exported Partition File (

.qxp

)

Timing

constraints

Clock properties, exceptions,

setup/hold

Tools 

➤

 Timing Analyzer

Synopsys Design Constraints File (

.sdc

)

Logic design

files

RTL and other design source

files

File 

➤

 New

All supported HDL files

Programming

files

Device programming image

and information

Tools 

➤

 Programmer

SRAM Object File (

.sof

)Programmer

Object File (

.pof

)

Project library

Project and global library

information

Tools 

➤

 Options 

➤

Libraries

.qsf

 (project)

quartus2.ini

 (global)

IP core files

IP core logic, synthesis, and

simulation information

Tools 

➤

 IP Catalog

Intel Quartus Prime IP File (

.qip

)

Platform

Designer

(Standard)

system files

Platform Designer

(Standard) system and IP

core files

Tools 

➤

 Platform

Designer (Standard)

Platform Designer (Standard) System
File (

.qsys

)

EDA tool files

Generated for third-party

EDA tools

Assignments 

➤

 Settings

➤

 EDA Tool Settings

Verilog Output File (

.vo

)

VHDL Output File (

.vho

)

Verilog Quartus Mapping File (

.vqm

)

Archive files

Complete project as single

compressed file

Project 

➤

 Archive Project

Intel Quartus Prime Archive File (

.qar

)

1.2 Viewing Basic Project Information

View basic information about your project in the Project Navigator, Report panel, and
Messages window. View project elements in the Project Navigator (View 

➤

 Utility

Windows 

➤

 Project Navigator). The Project Navigator displays key project

information, such as design files, IP components, and your project hierarchy. Use the

Project Navigator to locate and perform actions of the elements of your project. To

access the tabs of the Project Navigator, click the toggle control at the top of the

Project Navigator window.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

20

Table 2.

Project Navigator Tabs

Project Navigator Tab

Description

Files

Lists all design files in the current project. Right-click design files in this tab to

run these commands:
• Open the file
• Remove the file from project
• View file Properties
• Create AHDL Include Files for Currnt File
• Create Symbol Files for Current File
• Create Verilog Instantiation Template Files for Current File
• Create VHDL Component Declaration Files for Current File

Hierarchy

Provides a visual representation of the project hierarchy, specific resource usage

information, and device and device family information. Right-click items in the

hierarchy to Locate, Set as Top-Level Entity, or define Logic Lock regions or

design partitions.

Design Units

Displays the design units in the project. Right-click a design unit to Locate in

Design File.

IP Components

Displays the design files that make up the IP instantiated in the project,

including Intel FPGA IP, Platform Designer (Standard) components, and third-

party IP. Click Launch IP Upgrade Tool from this tab to upgrade outdated IP

components. Right-click any IP component to Edit in Parameter Editor.

Revisions

Displays the current project revisions.

1.2.1 Viewing Project Reports

The Compilation Report panel updates dynamically to display detailed reports during

project processing.

To access the Compilation Report, click (Processing 

➤

 Compilation Report).

•

Analysis & Synthesis reports

•

Fitter reports

•

Timing analysis reports

•

Power analysis reports

•

Signal integrity reports

Analyze the detailed project information in these reports to determine correct

implementation. Right-click report data to locate and edit the source in project files.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

21

Figure 2.

Compilation Report

Related Links
List of Compilation Reports

1.2.2 Viewing Project Messages

The Messages window (View 

➤

 Utility Windows 

➤

 Messages) displays information,

warning, and error messages about Intel Quartus Prime processes. Right-click

messages to locate the source or get message help.
•

Processing tab—displays messages from the most recent process

•

System tab—displays messages unrelated to design processing

•

Search—locates specific messages

Messages are written to 

stdout

 when you use command-line executables.

Figure 3.

Messages Window

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

22

You can suppress display of unimportant messages so they do not obscure valid

messages.

Figure 4.

Message Suppression by Message ID Number

1.2.2.1 Suppressing Messages

Suppress any messages that you do not want to view. To supress messages, right-

click a message and choose any of the following:

•

Suppress Message—suppresses all messages matching exact text

•

Suppress Messages with Matching ID—suppresses all messages matching the

message ID number, ignoring variables

•

Suppress Messages with Matching Keyword—suppresses all messages

matching keyword or hierarchy

1.2.2.2 Message Suppression Guidelines

•

You cannot suppress error or Intel legal agreement messages.

•

Suppressing a message also suppresses any submessages.

•

Message suppression is project revision-specific. Derivative project revisions

inherit any suppression.

•

You cannot edit messages or suppression rules during compilation.

1.3 Project Management Best Practices

The Intel Quartus Prime software provides various options for setting up a project. The

following best practices help ensure efficient management and portability of your

project files.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

23

Setting and Project File Best Practices

•

Be very careful if you edit any Intel Quartus Prime data files, such as the Intel
Quartus Prime Project File (

.qpf

), Intel Quartus Prime Settings File (

.qsf

),

Quartus IP File (

.qip

), or Platform Designer (Standard) System File (

.qsys

).

Typos in these files can cause software errors. For example, the software may

ignore settings and assignments.
Every Intel Quartus Prime project revision automatically includes a
supporting 

.qpf

 that preserves various project settings and constraints that you

enter in the GUI or add with Tcl commands. This file contains basic information

about the current software version, date, and project-wide and entity level
settings. Due to dependencies between the 

.qpf

 and 

.qsf

, avoid manually

editing 

.qsf

 files.

•

Do not compile multiple projects into the same directory. Instead, use a separate

directory for each project.

•

By default, the Intel Quartus Prime software saves all project output files, such as
Text-Format Report Files (

.rpt

), in the project directory. Instead of manually

moving project output files, change your project compilation settings to save them

in a separate directory.
To save these files into a different directory choose Assignments 

➤

 Settings 

➤

Compilation Process Settings. Turn on Save project output files in specified

directory and specify a directory for the output files.

Project Archive and Source Control Best Practices

Click Project 

➤

 Archive Project to archive your project for revision control.

As you develop your design, your Intel Quartus Prime project directory contains a

variety of source and settings files, compilation database files, output, and report files.

You can archive these files using the Archive feature and save the archive for later use

or place it under revision control.
1. Choose Project 

➤

 Archive Project 

➤

 Advanced to open the Advanced Archive

Settings dialog box.

2. Choose a file set to archive. For example, choose File set 

➤

 Source control with

incremental compilation and Rapid Recompile database to save the source

and database file required to re-create your project with your Rapid Recompile

revisions.

3. Add additional files by clicking Add (optional).

To restore your archived project, choose Project 

➤

 Restore Archived Project.

Restore your project into a new, empty directory.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

24

IP Core Best Practices

•

Do not manually edit or write your own 

.qsys

, 

.ip

, or 

.qip

 file. Use the Intel

Quartus Prime software tools to create and edit these files.
Note: When generating IP cores, do not generate files into a directory that has a

space in the directory name or path. Spaces are not legal characters for IP

core paths or names.

•

When you generate an IP core using the IP Catalog, the Intel Quartus Prime
software generates a 

.qsys

 (for Platform Designer (Standard)-generated IP

cores) or a 

.ip

 file (for Intel Quartus Prime Pro Edition) or a 

.qip

 file. The Intel

Quartus Prime Pro Edition software automatically adds the generated 

.ip

 to your

project. In the Intel Quartus Prime Standard Edition software, add the 

.qip

 to

your project. Do not add the parameter editor generated file (

.v

 or 

.vhd

) to your

design without the 

.qsys

 or 

.qip

 file. Otherwise, you cannot use the IP upgrade

or IP parameter editor feature.

•

Plan your directory structure ahead of time. Do not change the relative path
between a 

.qsys

 file and it's generation output directory. If you must move

the 

.qsys

 file, ensure that the generation output directory remains with

the 

.qsys

 file.

•

Do not add IP core files directly from the /quartus/libraries/megafunctions

directory in your project. Otherwise, you must update the files for each
subsequent software release. Instead, use the IP Catalog and then add the 

.qip

to your project.

•

Do not use IP files that the Intel Quartus Prime software generates for RAM or

FIFO blocks targeting older device families (even though the Intel Quartus Prime

software does not issue an error). The RAM blocks that Intel Quartus Prime

generates for older device families are not optimized for the latest device families.

•

When generating a ROM function, save the resulting 

.mif

 or 

.hex

 file in the same

folder as the corresponding IP core's 

.qsys

 or 

.qip

 file. For example, moving all

of your project's 

.mif

 or 

.hex

 files to the same directory causes relative path

problems after archiving the design.

•

Always use the Intel Quartus Prime 

ip-setup-simulation

 and 

ip-make-

simscript

 utilities to generate simulation scripts for each IP core or Platform

Designer (Standard) system in your design. These utilities produce a single

simulation script that does not require manual update for upgrades to Intel

Quartus Prime software or IP versions.

Related Links
Generating a Combined Simulator Setup Script

 on page 262

1.4 Managing Project Settings

The New Project Wizard guides you to make intial project settings when you setup a

new project. Optimizing project settings helps the Compiler to generate programming

files that meet or exceed your specifications.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

25

On the Tasks pane, click Settings to access global project settings, including:
•

Project files list

•

Synthesis directives and constraints

•

Logic options and compiler effort levels

•

Placement constraints

•

Timing constraint files

•

Operating temperature limits and conditions

•

File generation for other EDA tools

•

Target a device (click Device)

•

Target a development kit

The 

.qsf

 stores each project revision’s project settings. The Intel Quartus Prime

Default Settings File (<revision name>

_assignment_defaults.qdf

) stores the

default settings and constraints for each new project revision.

Figure 5.

Settings Dialog Box for Global Project Settings

The Assignment Editor (Tools > Assignment Editor) provides a spreadsheet-like

interface for assigning all instance-specific settings and constraints.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

26

Figure 6.

Assignment Editor Spreadsheet

1.4.1 Optimizing Project Settings

Optimize project settings to meet your design goals. The Intel Quartus Prime Design

Space Explorer II iteratively compiles your project with various setting combinations

to find the optimal setting for your goals. Alternatively, you can create a project

revision or project copy to manually compare various project settings and design

combinations.

The Intel Quartus Prime software includes several advisors to help you optimize your
design and reduce compilation time. The advisors listed in the Tools 

➤

 Advisors

menu can provide recommendations based on your project settings and design

constraints.

1.4.1.1 Optimizing with Design Space Explorer II

Use Design Space Explorer II (Tools > Launch Design Space Explorer II) to find

optimal project settings for resource, performance, or power optimization goals.

Design Space Explorer II (DSE II) processes your design using various setting and

constraint combinations, and reports the best settings for your design.

DSE II attempts multiple seeds to identify one meeting your requirements. DSE II can

run different compilations on multiple computers in parallel to streamline timing

closure.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

27

Figure 7.

Design Space Explorer II

1.4.1.2 Optimizing with Project Revisions

You can save multiple, named project revisions within your Intel Quartus Prime project

(Project > Revisions).

Each revision captures a unique set of project settings and constraints, but does not

capture any logic design file changes. Use revisions to experiment with different

settings while preserving the original. Optimize different revisions for various

applications. Use revisions for the following:
•

Create a unique revision to optimize a design for different criteria, such as by area

in one revision and by f

MAX

 in another revision.

•

When you create a new revision the default Intel Quartus Prime settings initially

apply.

•

Create a revision of a revision to experiment with settings and constraints. The

child revision includes all the assignments and settings of the parent revision.

You create, delete, and edit revisions in the Revisions dialog box. Each time you
create a new project revision, the Intel Quartus Prime software creates a new 

.qsf

using the revision name.

To compare each revision’s synthesis, fitting, and timing analysis results side-by-side,

click Project > Revisions and then click Compare.

In addition to viewing the compilation results of each revision, you can also compare

the assignments for each revision. This comparison reveals how different optimization

options affect your design.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

28

Figure 8.

Comparing Project Revisions

1.4.1.3 Copying Your Project

Click Project > Copy Project to create a separate copy of your project, rather than

just a revision within the same project.

The project copy includes all design files, any 

.qsf

 files, and project revisions. Use

this technique to optimize project copies for different applications. For example,

optimize one project to interface with a 32-bit data bus, and optimize a project copy

to interface with a 64-bit data bus.

1.4.1.4 Copy (Back-Annotate) Compiler Assignments

The Compiler maps the elements of your design to specific device and resource during

fitting. Following compilation, you can copy the Compiler's device and resource
assignments to the 

.qsf

 to preserve that same implementation in subsequent

compilations.

Click Assignments 

➤

 Back-Annoate Assignments to apply the device resource

assignments to the 

.qsf

. Select the back-annotation type in the Back-annotation

type list.

1.5 Managing Logic Design Files

The Intel Quartus Prime software helps you create and manage the logic design files in

your project. Logic design files contain the logic that implements your design. When

you add a logic design file to the project, the Compiler automatically compiles that file

as part of the project. The Compiler synthesizes your logic design files to generate

programming files for your target device.

The Intel Quartus Prime software includes full-featured schematic and text editors, as

well as HDL templates to accelerate your design work. The Intel Quartus Prime
software supports VHDL Design Files (

.vhd

), Verilog HDL Design Files (

.v

),

SystemVerilog (

.sv

) and schematic Block Design Files (

.bdf

). The Intel Quartus

Prime software also supports Verilog Quartus Mapping (

.vqm

) design files generated

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

29

by other design entry and synthesis tools. In addition, you can combine your logic

design files with Intel and third-party IP core design files, including combining
components into a Platform Designer (Standard) system (

.qsys

).

The New Project Wizard prompts you to identify logic design files. Add or remove

project files by clicking Project > Add/Remove Files in Project. View the project’s

logic design files in the Project Navigator.

Figure 9.

Design and IP Files in Project Navigator

Right-click files in the Project Navigator to:
•

Open and edit the file

•

Remove File from Project

•

Set as Top-Level Entity for the project revision

•

Create a Symbol File for Current File for display in schematic editors

•

Edit file Properties

1.5.1 Including Design Libraries

Include design files libraries in your project. Specify libraries for a single project, or for
all Intel Quartus Prime projects. The 

.qsf

 stores project library information.

The 

quartus2.ini

 file stores global library information.

Related Links
Design Library Migration Guidelines

 on page 66

1.5.1.1 Specifying Design Libraries

Follow these steps to specify project libraries from the GUI.
1. Click Assignment > Settings.
2. Click Libraries and specify the Project Library name or Global Library name.

Alternatively, you can specify project libraries with 

SEARCH_PATH

 in the 

.qsf

,

and global libraries in the 

quartus2.ini

 file.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

30

1.6 Managing Timing Constraints

Apply appropriate timing constraints to correctly optimize fitting and analyze timing

for your design. The Fitter optimizes the placement of logic in the device to meet your

specified timing and routing constraints.

Specify timing constraints in the Timing Analyzer (Tools > Timing Analyzer), or in
an 

.sdc

 file. Specify constraints for clock characteristics, timing exceptions, and

external signal setup and hold times before running analysis. Timing Analyzer reports

the detailed information about the performance of your design compared with

constraints in the Compilation Report panel.

Save the constraints you specify in the GUI in an industry-standard Synopsys Design
Constraints File (

.sdc

). You can subsequently edit the text-based 

.sdc

 file directly. If

you refer to multiple 

.sdc

 files in a parent 

.sdc

 file, the Timing Analyzer reads

the 

.sdc

 files in the order you list.

Figure 10.

Timing Analyzer and SDC Syntax Example

1.7 Introduction to Intel FPGA IP Cores

Intel and strategic IP partners offer a broad portfolio of configurable IP cores

optimized for Intel FPGA devices.

The Intel Quartus Prime software installation includes the Intel FPGA IP library.

Integrate optimized and verified Intel FPGA IP cores into your design to shorten design

cycles and maximize performance. The Intel Quartus Prime software also supports

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

31

integration of IP cores from other sources. Use the IP Catalog (Tools 

➤

 IP Catalog)

to efficiently parameterize and generate synthesis and simulation files for your custom

IP variation. The Intel FPGA IP library includes the following types of IP cores:
•

Basic functions

•

DSP functions

•

Interface protocols

•

Low power functions

•

Memory interfaces and controllers

•

Processors and peripherals

This document provides basic information about parameterizing, generating,

upgrading, and simulating stand-alone IP cores in the Intel Quartus Prime software.

Figure 11.

IP Catalog

Display All IP or by Device

Double-Click for Parameters
Right-Click for IP Details

Search for IP

1.7.1 IP Catalog and Parameter Editor

The IP Catalog displays the IP cores available for your project. Use the following

features of the IP Catalog to locate and customize an IP core:

•

Filter IP Catalog to Show IP for active device family or Show IP for all

device families. If you have no project open, select the Device Family in IP

Catalog.

•

Type in the Search field to locate any full or partial IP core name in IP Catalog.

•

Right-click an IP core name in IP Catalog to display details about supported

devices, to open the IP core's installation folder, and for links to IP documentation.

•

Click Search for Partner IP to access partner IP information on the web.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

32

The parameter editor generates a top-level Quartus IP file (

.qip

) for an IP variation

in Intel Quartus Prime Standard Edition projects. These files represent the IP variation

in the project, and store parameterization information.

Figure 12.

IP Parameter Editor (Intel Quartus Prime Standard Edition)

IP Port and 
Parameter
Details

Specify IP Variation Name
and Target Device

Related Links
Creating a System with Platform Designer (Standard)

 on page 198

1.7.1.1 The Parameter Editor

The parameter editor helps you to configure IP core ports, parameters, and output file

generation options. The basic parameter editor controls include the following:

•

Use the Presets window to apply preset parameter values for specific applications

(for select cores).

•

Use the Details window to view port and parameter descriptions, and click links to

documentation.

•

Click Generate 

➤

 Generate Testbench System to generate a testbench system

(for select cores).

•

Click Generate 

➤

 Generate Example Design to generate an example design

(for select cores).

The IP Catalog is also available in Platform Designer (View 

➤

 IP Catalog). The

Platform Designer IP Catalog includes exclusive system interconnect, video and image

processing, and other system-level IP that are not available in the Intel Quartus Prime

IP Catalog. Refer to Creating a System with Platform Designer or Creating a System

with Platform Designer (Standard) for information on use of IP in Platform Designer

(Standard) and Platform Designer, respectively.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

33

Related Links

•

Creating a System with Platform Designer

•

Creating a System with Platform Designer (Standard)

1.7.1.2 Adding IP Cores to IP Catalog

The IP Catalog automatically displays IP cores located in the project directory, in the

default Intel Quartus Prime installation directory, and in the IP search path.

Figure 13.

Specifying IP Search Locations

Add a Global 

IP Search Path

Add a Project-
Specific Search Path

The IP Catalog displays Intel Quartus Prime IP components and Platform Designer

systems, third-party IP components, and any custom IP components that you include
in the path. Use the IP Search Path option (Tools 

➤

 Options) to include custom

and third-party IP components in the IP Catalog.

The Intel Quartus Prime software searches the directories listed in the IP search path

for the following IP core files:
•

Component Description File (

_hw.tcl

)—defines a single IP core.

•

IP Index File (

.ipx

)—each 

.ipx

 file indexes a collection of available IP cores. This

file specifies the relative path of directories to search for IP cores. In
general, 

.ipx

 files facilitate faster searches.

The Intel Quartus Prime software searches some directories recursively and other

directories only to a specific depth. When the search is recursive, the search stops at
any directory that contains a 

_hw.tcl

 or 

.ipx

 file.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

34

In the following list of search locations, ** indicates a recursive descent.

Table 3.

IP Search Locations

Location

Description

PROJECT_DIR/*

Finds IP components and index files in the Intel Quartus Prime project directory.

PROJECT_DIR/ip/**/*

Finds IP components and index files in any subdirectory of the 

/ip

 subdirectory of the Intel

Quartus Prime project directory.

If the Intel Quartus Prime software recognizes two IP cores with the same name, the

following search path precedence rules determine the resolution of files:
1. Project directory.
2. Project database directory.
3. Project IP search path specified in IP Search Locations, or with the

SEARCH_PATH

 assignment for the current project revision.

4. Global IP search path specified in IP Search Locations, or with the

SEARCH_PATH

 assignment in the 

quartus2.ini

 file.

5. Quartus software libraries directory, such as 

<Quartus Installation>

\libraries

.

Note: 

If you add an IP component to the search path, update the IP Catalog by clicking

Refresh IP Catalog in the drop-down list. In Platform Designer (Standard) and
Platform Designer, click File 

➤

 Refresh System to update the IP Catalog.

1.7.1.3 General Settings for IP

Use the following settings to control how the Intel Quartus Prime software manages IP

cores in your project.

Table 4.

IP Core General Setting Locations

Setting Location

Description

Tools 

➤

 Options 

➤

 IP Settings

Or

• Specify the IP generation HDL preference. The parameter editor

generates the HDL you specify for IP variations.

• Increase the Maximum Platform Designer memory usage size if

you experience slow processing for large systems, or for out of memory

errors.

• Specify whether to Automatically add Intel Quartus Prime IP files

to all projects. Disable this option to manually add the IP files.

• Use the IP Regeneration Policy setting to control when synthesis files

regenerate for each IP variation. Typically, you Always regenerate

synthesis files for IP cores after making changes to an IP variation.

Tools 

➤

 Options 

➤

 IP Catalog Search

Locations
Or

• Specify additional project and global IP search locations. The Intel

Quartus Prime software searches for IP cores in the project directory, in

the Intel Quartus Prime installation directory, and in the IP search path.

1.7.1.4 Installing and Licensing Intel FPGA IP Cores

The Intel Quartus Prime software installation includes the Intel FPGA IP library. This

library provides many useful IP cores for your production use without the need for an

additional license. Some Intel FPGA IP cores require purchase of a separate license for

production use. The Intel FPGA IP Evaluation Mode allows you to evaluate these

licensed Intel FPGA IP cores in simulation and hardware, before deciding to purchase a

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

35

full production IP core license. You only need to purchase a full production license for

licensed Intel IP cores after you complete hardware testing and are ready to use the

IP in production.

The Intel Quartus Prime software installs IP cores in the following locations by default:

Figure 14.

IP Core Installation Path

intelFPGA(_pro)

quartus - 

Contains the Intel Quartus Prime software

ip - 

Contains the Intel FPGA IP library and third-party IP cores

altera - 

Contains the Intel FPGA IP library source code

<IP name>

 - Contains the Intel FPGA IP source files  

Table 5.

IP Core Installation Locations

Location

Software

Platform

<drive>:\intelFPGA_pro\quartus\ip\altera

Intel Quartus Prime Pro Edition

Windows*

<drive>:\intelFPGA\quartus\ip\altera

Intel Quartus Prime Standard

Edition

Windows

<home directory>:/intelFPGA_pro/quartus/ip/altera

Intel Quartus Prime Pro Edition

Linux*

<home directory>:/intelFPGA/quartus/ip/altera

Intel Quartus Prime Standard

Edition

Linux

1.7.1.4.1 Intel FPGA IP Evaluation Mode

The free Intel FPGA IP Evaluation Mode allows you to evaluate licensed Intel FPGA IP

cores in simulation and hardware before purchase. Intel FPGA IP Evaluation Mode

supports the following evaluations without additional license:

•

Simulate the behavior of a licensed Intel FPGA IP core in your system.

•

Verify the functionality, size, and speed of the IP core quickly and easily.

•

Generate time-limited device programming files for designs that include IP cores.

•

Program a device with your IP core and verify your design in hardware.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

36

Intel FPGA IP Evaluation Mode supports the following operation modes:
•

Tethered—Allows running the design containing the licensed Intel FPGA IP

indefinitely with a connection between your board and the host computer.

Tethered mode requires a serial joint test action group (JTAG) cable connected

between the JTAG port on your board and the host computer, which is running the

Intel Quartus Prime Programmer for the duration of the hardware evaluation

period. The Programmer only requires a minimum installation of the Intel Quartus

Prime software, and requires no Intel Quartus Prime license. The host computer

controls the evaluation time by sending a periodic signal to the device via the

JTAG port. If all licensed IP cores in the design support tethered mode, the

evaluation time runs until any IP core evaluation expires. If all of the IP cores

support unlimited evaluation time, the device does not time-out.

•

Untethered—Allows running the design containing the licensed IP for a limited

time. The IP core reverts to untethered mode if the device disconnects from the

host computer running the Intel Quartus Prime software. The IP core also reverts

to untethered mode if any other licensed IP core in the design does not support

tethered mode.

When the evaluation time expires for any licensed Intel FPGA IP in the design, the

design stops functioning. All IP cores that use the Intel FPGA IP Evaluation Mode time

out simultaneously when any IP core in the design times out. When the evaluation

time expires, you must reprogram the FPGA device before continuing hardware

verification. To extend use of the IP core for production, purchase a full production

license for the IP core.

You must purchase the license and generate a full production license key before you

can generate an unrestricted device programming file. During Intel FPGA IP Evaluation

Mode, the Compiler only generates a time-limited device programming file (<project
name>

_time_limited.sof

) that expires at the time limit.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

37

Figure 15.

Intel FPGA IP Evaluation Mode Flow

Install the Intel Quartus Prime 

Software with Intel FPGA IP Library

Parameterize and Instantiate a

Licensed Intel FPGA IP Core

Purchase a Full Production

 IP License

Verify the IP in a 

Supported Simulator

Compile the Design in the

Intel Quartus Prime Software

Generate a Time-Limited Device

Programming File

Program the Intel FPGA Device

and Verify Operation on the Board

No

Yes

IP Ready for

Production Use?

Include Licensed IP 

in Commercial Products

Note: 

Refer to each IP core's user guide for parameterization steps and implementation

details.

Intel licenses IP cores on a per-seat, perpetual basis. The license fee includes first-

year maintenance and support. You must renew the maintenance contract to receive

updates, bug fixes, and technical support beyond the first year. You must purchase a

full production license for Intel FPGA IP cores that require a production license, before

generating programming files that you may use for an unlimited time. During Intel

FPGA IP Evaluation Mode, the Compiler only generates a time-limited device
programming file (<project name>

_time_limited.sof

) that expires at the time

limit. To obtain your production license keys, visit the 

Self-Service Licensing Center

 or

contact your local 

Intel FPGA representative

.

The 

Intel FPGA Software License Agreements

 govern the installation and use of

licensed IP cores, the Intel Quartus Prime design software, and all unlicensed IP cores.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

38

Related Links

•

Intel Quartus Prime Licensing Site

•

Intel FPGA Software Installation and Licensing

1.7.2 Generating IP Cores (Intel Quartus Prime Standard Edition)

This topic describes parameterizing and generating an IP variation using a legacy

parameter editor in the Intel Quartus Prime Standard Edition software.

Figure 16.

Legacy Parameter Editors

Note: 

The legacy parameter editor generates a different output file structure than the Intel

Quartus Prime Pro Edition software.

1. In the IP Catalog (Tools 

➤

 IP Catalog), locate and double-click the name of the

IP core to customize. The parameter editor appears.

2. Specify a top-level name and output HDL file type for your IP variation. This name

identifies the IP core variation files in your project. Click OK. Do not include

spaces in IP variation names or paths.

3. Specify the parameters and options for your IP variation in the parameter editor.

Refer to your IP core user guide for information about specific IP core parameters.

4. Click Finish or Generate (depending on the parameter editor version). The

parameter editor generates the files for your IP variation according to your

specifications. Click Exit if prompted when generation is complete. The parameter
editor adds the top-level 

.qip

 file to the current project automatically.

Note: For devices released prior to Intel Arria

®

 10 devices, the generated 

.qip

and 

.sip

 files must be added to your project to represent IP and Platform

Designer systems. To manually add an IP variation generated with legacy
parameter editor to a project, click Project 

➤

 Add/Remove Files in

Project and add the IP variation 

.qip

 file.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

39

1.7.2.1 IP Core Generation Output (Intel Quartus Prime Standard Edition)

The Intel Quartus Prime Standard Edition software generates one of the following

output file structures for individual IP cores that use one of the legacy parameter

editors.

Figure 17.

IP Core Generated Files (Legacy Parameter Editors)

Generated IP File Output B 

<Project Directory>

<your_ip>

.html

 - IP core generation report

<your_ip>

_testbench.v

 or 

.vhd 

- Testbench file

1

<your_ip>

.bsf

 - Block symbol schematic file 

<your_ip>

_syn.v

 or 

.vhd

 - Timing & resource estimation netlist1 

<your_ip>

_bb

 - Verilog HDL black box EDA synthesis file

<your_ip>

.vo

 or 

.vho

 - IP functional simulation model 2

<your_ip>

.qip

 - Intel Quartus Prime IP integration file

<your_ip>

.v

 or 

.vhd

 - Top-level HDL IP variation definition 

<your_ip>

_block_period_stim.txt

 - Testbench simulation data 

1

<your_ip>

-library

 

- Contains IP subcomponent synthesis libraries

Generated IP File Output A  

<Project Directory>

  

<

your_ip>

.v

 or 

.vhd

 - Top-level IP synthesis file 

<your_ip>

_inst.v

 or 

.vhd

 - Sample instantiation template 

<your_ip>

.bsf

 - Block symbol schematic file 

<your_ip>

.vo

 or 

.vho

 - IP functional simulation model 2

<your_ip>

_syn.v

 or 

.vhd

 - Timing & resource estimation netlist1 

<your_ip>

_bb.v

 - Verilog HDL black box EDA synthesis file

<your_ip>

.qip

 - Intel Quartus Prime IP integration file

greybox_tmp 

3

  

<your_ip>

.cmp

 - VHDL component declaration file 

Generated IP File Output C 

<Project Directory>

<your_ip>

_sim

 1

<IP>

_instance.vo

 - IPFS model 2

<simulator_vendor>

<simulator setup scripts>

<your_ip>

.qip

 - Intel Quartus Prime IP integration file

<your_ip>

.sip

 - Lists files for simulation 

<your_ip>

_testbench

 or 

_example

 

- Testbench or example1

<your_ip>

.v

, 

.sv

. or 

.vhd

 - Top-level IP synthesis file 

<IP_name>

_instance

<your_ip>

_syn.v

 or 

.vhd

 - Timing & resource estimation netlist1

<your_ip>

.cmp

 - VHDL component declaration file 

<your_ip>

.bsf

 - Block symbol schematic file 

<your_ip>

 - IP core synthesis files

<your_ip>

.sv

, 

.v

, or 

.vhd

 - HDL synthesis files

<your_ip>

.sdc

 - Timing constraints file

<your_ip>

.ppf

 - XML I/O pin information file

<your_ip>

.spd

 - Combines individual simulation scripts

 1

<your_ip>

_sim.f

 - Refers to simulation models and scripts 

1

Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated
3. Ignore this directory 

Generated IP File Output D 

<Project Directory>

<your_ip>

_bb.v

 - Verilog HDL black box EDA synthesis file

<your_ip>

_inst.v

 or 

.vhd

 - Sample instantiation template 

synthesis - IP synthesis files

<your_ip>

.qip

 - Lists files for synthesis

testbench - Simulation testbench files

 

1

<testbench_hdl_files>

<simulator_vendor>

 - Testbench for supported simulators

<simulation_testbench_files>

<your_ip>

.v

 or 

.vhd

 - Top-level IP variation synthesis file

simulation - IP simulation files

<your_ip>

.sip

 - NativeLink simulation integration file

<simulator vendor>

 - Simulator setup scripts

<simulator_setup_scripts>

<your_ip>

 - IP core variation files

<your_ip>

.qip

 or 

.qsys

 - System or IP integration file

<your_ip>

_generation.rpt

 - IP generation report

<your_ip>

.bsf

 - Block symbol schematic file 

<your_ip>

.ppf

 - XML I/O pin information file

<your_ip>

.spd

 - Combines individual simulation startup scripts

 1

<your_ip>

.html

 - Contains memory map

<your_ip>

.sopcinfo

 - Software tool-chain integration file

<your_ip>

_syn.v

 or 

.vhd

 - Timing & resource estimation netlist 1

<your_ip>

.debuginfo

 - Lists files for synthesis

<your_ip>

.v

, .

vhd,

 

.vo

, 

.vho

 - HDL or IPFS models

2

<your_ip>

_tb

 - Testbench for supported simulators

<your_ip>

_tb.v

 or 

.vhd

 - Top-level HDL testbench file

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

40

1.7.3 Modifying an IP Variation

After generating an IP core variation, use any of the following methods to modify the

IP variation in the parameter editor.

Table 6.

Modifying an IP Variation

Menu Command

Action

File 

➤

 Open

Select the top-level HDL (

.v

, or 

.vhd

) IP variation file to launch the

parameter editor and modify the IP variation. Regenerate the IP

variation to implement your changes.

View 

➤

 Utility Windows 

➤

 Project Navigator 

➤

IP Components

Double-click the IP variation to launch the parameter editor and

modify the IP variation. Regenerate the IP variation to implement

your changes.

Project 

➤

 Upgrade IP Components

Select the IP variation and click Upgrade in Editor to launch the

parameter editor and modify the IP variation. Regenerate the IP

variation to implement your changes.

1.7.4 Upgrading IP Cores

Any Intel FPGA IP variations that you generate from a previous version or different

edition of the Intel Quartus Prime software, may require upgrade before compilation in

the current software edition or version. The Project Navigator displays a banner
indicating the IP upgrade status. Click Launch IP Upgrade Tool or Project 

➤

Upgrade IP Components to upgrade outdated IP cores.

Figure 18.

IP Upgrade Alert in Project Navigator

Icons in the Upgrade IP Components dialog box indicate when IP upgrade is

required, optional, or unsupported for an IP variation in the project. Upgrade IP

variations that require upgrade before compilation in the current version of the Intel

Quartus Prime software.

Note: 

Upgrading IP cores may append a unique identifier to the original IP core entity

names, without similarly modifying the IP instance name. There is no requirement to

update these entity references in any supporting Intel Quartus Prime file, such as the
Intel Quartus Prime Settings File (

.qsf

), Synopsys* Design Constraints File (

.sdc

),

or Signal Tap File (

.stp

), if these files contain instance names. The Intel Quartus

Prime software reads only the instance name and ignores the entity name in paths

that specify both names. Use only instance names in assignments.

Table 7.

IP Core Upgrade Status

IP Core Status

Description

IP Upgraded

Indicates that your IP variation uses the latest version of the Intel FPGA IP core.

continued...   

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

41

IP Core Status

Description

 

 

IP Component Outdated

 

 

Indicates that your IP variation uses an outdated version of the IP core.

IP Upgrade Optional

 

 

Indicates that upgrade is optional for this IP variation in the current version of the Intel

Quartus Prime software. You can upgrade this IP variation to take advantage of the latest

development of this IP core. Alternatively, you can retain previous IP core characteristics by

declining to upgrade. Refer to the Description for details about IP core version differences.

If you do not upgrade the IP, the IP variation synthesis and simulation files are unchanged

and you cannot modify parameters until upgrading.

IP Upgrade Required

 

 

Indicates that you must upgrade the IP variation before compiling in the current version of

the Intel Quartus Prime software. Refer to the Description for details about IP core version

differences.

IP Upgrade Unsupported

 

 

Indicates that upgrade of the IP variation is not supported in the current version of the

Intel Quartus Prime software due to incompatibility with the current version of the Intel

Quartus Prime software. The Intel Quartus Prime software prompts you to replace the

unsupported IP core with a supported equivalent IP core from the IP Catalog. Refer to the

Description for details about IP core version differences and links to Release Notes.

IP End of Life

 

 

Indicates that Intel designates the IP core as end-of-life status. You may or may not be

able to edit the IP core in the parameter editor. Support for this IP core discontinues in

future releases of the Intel Quartus Prime software.

IP Upgrade Mismatch

Warning

 

 

Provides warning of non-critical IP core differences in migrating IP to another device family.

IP has incompatible subcores

 

 

Indicates that the current version of the Intel Quartus Prime software does not support

compilation of your IP variation, because the IP has incompatible subcores

Compilation of IP Not

Supported

 

 

Indicates that the current version of the Intel Quartus Prime software does not support

compilation of your IP variation. This can occur if another edition of the Intel Quartus Prime

software generated this IP. Replace this IP component with a compatible component in the

current edition.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

42

Follow these steps to upgrade IP cores:
1. In the latest version of the Intel Quartus Prime software, open the Intel Quartus

Prime project containing an outdated IP core variation. The Upgrade IP

Components dialog box automatically displays the status of IP cores in your

project, along with instructions for upgrading each core. To access this dialog box
manually, click Project 

➤

 Upgrade IP Components.

2. To upgrade one or more IP cores that support automatic upgrade, ensure that you

turn on the Auto Upgrade option for the IP cores, and click Perform Automatic

Upgrade. The Status and Version columns update when upgrade is complete.

Example designs that any Intel FPGA IP core provides regenerate automatically

whenever you upgrade an IP core.

3. To manually upgrade an individual IP core, select the IP core and click Upgrade in

Editor (or simply double-click the IP core name). The parameter editor opens,

allowing you to adjust parameters and regenerate the latest version of the IP core.

Figure 19.

Upgrading IP Cores

Runs “Auto Upgrade” on all Outdated Cores

Opens Editor for Manual IP Upgrade

Upgrade Details

Generates/Updates Combined Simulation Setup Script for all Project IP

Note: Intel FPGA IP cores older than Intel Quartus Prime software version 12.0 do

not support upgrade. Intel verifies that the current version of the Intel

Quartus Prime software compiles the previous two versions of each IP core.

The Intel FPGA IP Core Release Notes reports any verification exceptions for

Intel FPGA IP cores. Intel does not verify compilation for IP cores older than

the previous two releases.

Related Links
Intel FPGA IP Core Release Notes

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

43

1.7.4.1 Upgrading IP Cores at Command-Line

Optionally, upgrade an Intel FPGA IP core at the command-line, rather than using the

GUI. IP cores that do not support automatic upgrade do not support command-line

upgrade.

•

To upgrade a single IP core at the command-line, type the following command:

quartus_sh –ip_upgrade –variation_files 

<my_ip>.<qsys,.v, .vhd> 

<quartus_project>

Example:
quartus_sh -ip_upgrade -variation_files 

mega/pll25.qsys hps_testx

•

To simultaneously upgrade multiple IP cores at the command-line, type the

following command:

quartus_sh –ip_upgrade –variation_files “

<my_ip1>

.

<qsys,.v, .vhd>>

;  

<my_ip_filepath/my_ip2>.<hdl>”  <quartus_project>

Example:
quartus_sh -ip_upgrade -variation_files "

mega/pll_tx2.qsys;mega/

pll3.qsys" hps_testx

1.7.4.2 Migrating IP Cores to a Different Device

Migrate an Intel FPGA IP variation when you want to target a different (often newer)

device. Most Intel FPGA IP cores support automatic migration. Some IP cores require

manual IP regeneration for migration. A few IP cores do not support device migration,

requiring you to replace them in the project. The Upgrade IP Components dialog

box identifies the migration support level for each IP core in the design.
1. To display the IP cores that require migration, click Project 

➤

 Upgrade IP

Components. The Description field provides migration instructions and version

differences.

2. To migrate one or more IP cores that support automatic upgrade, ensure that the

Auto Upgrade option is turned on for the IP cores, and click Perform Automatic

Upgrade. The Status and Version columns update when upgrade is complete.

3. To migrate an IP core that does not support automatic upgrade, double-click the

IP core name, and click OK. The parameter editor appears. If the parameter editor

specifies a Currently selected device family, turn off Match project/default,

and then select the new target device family.

4. Click Generate HDL, and confirm the Synthesis and Simulation file options.

Verilog HDL is the default output file format. If you specify VHDL as the output

format, select VHDL to retain the original output format.

5. Click Finish to complete migration of the IP core. Click OK if the software prompts

you to overwrite IP core files. The Device Family column displays the new target

device name when migration is complete.

6. To ensure correctness, review the latest parameters in the parameter editor or

generated HDL.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

44

Note: IP migration may change ports, parameters, or functionality of the IP

variation. These changes may require you to modify your design or to re-

parameterize your IP variant. During migration, the IP variation's HDL

generates into a library that is different from the original output location of

the IP core. Update any assignments that reference outdated locations. If a

symbol in a supporting Block Design File schematic represents your

upgraded IP core, replace the symbol with the newly generated
<my_ip>

.bsf

. Migration of some IP cores requires installed support for the

original and migration device families.

Related Links
Intel FPGA IP Release Notes

1.7.4.3 Troubleshooting IP or Platform Designer System Upgrade

The Upgrade IP Components dialog box reports the version and status of each IP

core and Platform Designer system following upgrade or migration.

If any upgrade or migration fails, the Upgrade IP Components dialog box provides

information to help you resolve any errors.

Note: 

Do not use spaces in IP variation names or paths.

During automatic or manual upgrade, the Messages window dynamically displays

upgrade information for each IP core or Platform Designer system. Use the following

information to resolve upgrade errors:

Table 8.

IP Upgrade Error Information

Upgrade IP Components

Field

Description

Status

Displays the "Success" or "Failed" status of each upgrade or migration. Click the status of

any upgrade that fails to open the IP Upgrade Report.

Version

Dynamically updates the version number when upgrade is successful. The text is red when

the IP requires upgrade.

Device Family

Dynamically updates to the new device family when migration is successful. The text is red

when the IP core requires upgrade.

Auto Upgrade

Runs automatic upgrade on all IP cores that support auto upgrade. Also, automatically
generates a 

<Project Directory>

/

ip_upgrade_port_diff_report

 report for IP

cores or Platform Designer systems that fail upgrade. Review these reports to determine

any port differences between the current and previous IP core version.

Use the following techniques to resolve errors if your IP core or Platform Designer

system "Failed" to upgrade versions or migrate to another device. Review and

implement the instructions in the Description field, including one or more of the

following:

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

45

•

If the current version of the software does not support the IP variant, right-click

the component and click Remove IP Component from Project. Replace this IP

core or Platform Designer system with the one supported in the current version of

the software.

•

If the current target device does not support the IP variant, select a supported

device family for the project, or replace the IP variant with a suitable replacement

that supports your target device.

•

If an upgrade or migration fails, click Failed in the Status field to display and

review details of the IP Upgrade Report. Click the Release Notes link for the

latest known issues about the IP core. Use this information to determine the

nature of the upgrade or migration failure and make corrections before upgrade.

•

Run Auto Upgrade to automatically generate an IP Ports Diff report for each IP

core or Platform Designer system that fails upgrade. Review the reports to

determine any port differences between the current and previous IP core version.

Click Upgrade in Editor to make specific port changes and regenerate your IP

core or Platform Designer system.

•

If your IP core or Platform Designer system does not support Auto Upgrade, click

Upgrade in Editor to resolve errors and regenerate the component in the

parameter editor.

Figure 20.

IP Upgrade Report

Reports on Failed

IP Upgrades

Report Summary

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

46

1.7.5 Simulating Intel FPGA IP Cores

The Intel Quartus Prime software supports IP core RTL simulation in specific EDA

simulators. IP generation creates simulation files, including the functional simulation

model, any testbench (or example design), and vendor-specific simulator setup scripts

for each IP core. Use the functional simulation model and any testbench or example

design for simulation. IP generation output may also include scripts to compile and run

any testbench. The scripts list all models or libraries you require to simulate your IP

core.

The Intel Quartus Prime software provides integration with many simulators and

supports multiple simulation flows, including your own scripted and custom simulation

flows. Whichever flow you choose, IP core simulation involves the following steps:
1. Generate simulation model, testbench (or example design), and simulator setup

script files.

2. Set up your simulator environment and any simulation scripts.
3. Compile simulation model libraries.
4. Run your simulator.

1.7.5.1 Generating IP Simulation Files

The Intel Quartus Prime software optionally generates the functional simulation model,

any testbench (or example design), and vendor-specific simulator setup scripts when

you generate an IP core. To control the generation of IP simulation files:

•

To specify your supported simulator and options for IP simulation file generation,
click Assignment 

➤

 Settings 

➤

 EDA Tool Settings 

➤

 Simulation.

•

To parameterize a new IP variation, enable generation of simulation files, and
generate the IP core synthesis and simulation files, click Tools 

➤

 IP Catalog.

•

To edit parameters and regenerate synthesis or simulation files for an existing IP
core variation, click View 

➤

 Utility Windows 

➤

 Project Navigator 

➤

 IP

Components.

Table 9.

Intel FPGA IP Simulation Files

File Type

Description

File Name

Simulator setup

scripts

Vendor-specific scripts to compile, elaborate, and simulate

Intel FPGA IP models and simulation model library files.

Optionally, generate a simulator setup script for each

vendor that combines the individual IP core scripts into one

file. Source the combined script from your top-level

simulation script to eliminate script maintenance.

<my_dir>/aldec/

rivierapro_setup.tcl

<my_dir>/cadence/

ncsim_setup.sh

<my_dir>/mentor/msim_setup.tcl

continued...   

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

47

File Type

Description

File Name

<my_dir>/synopsys/vcs/

vcs_setup.sh

Simulation IP File

(Intel Quartus

Prime Standard

Edition)

Contains IP core simulation library mapping information. To
use NativeLink, add the 

.qip

 and 

.sip

 files generated for

IP to your project.

<design name>.sip

IP functional

simulation models

(Intel Quartus

Prime Standard

Edition)

IP functional simulation models are cycle-accurate VHDL or

Verilog HDL models a that the Intel Quartus Prime software

generates for some Intel FPGA IP cores. IP functional

simulation models support fast functional simulation of IP

using industry-standard VHDL and Verilog HDL simulators.

<my_ip>.vho

<my_ip>.vo

IEEE encrypted

models (Intel

Quartus Prime

Standard Edition)

Intel provides Arria V, Cyclone

®

 V, Stratix

®

 V, and newer

simulation model libraries and IP simulation models in

Verilog HDL and IEEE-encrypted Verilog HDL. Your

simulator's co-simulation capabilities support VHDL

simulation of these models. IEEE encrypted Verilog HDL

models are significantly faster than IP functional simulation

models. The Intel Quartus Prime Pro Edition software does

not support these models.

<my_ip>.v

Note: 

Intel FPGA IP cores support a variety of cycle-accurate simulation models, including

simulation-specific IP functional simulation models and encrypted RTL models, and

plain text RTL models. The models support fast functional simulation of your IP core

instance using industry-standard VHDL or Verilog HDL simulators. For some IP cores,

generation only produces the plain text RTL model, and you can simulate that model.

Use the simulation models only for simulation and not for synthesis or any other

purposes. Using these models for synthesis creates a nonfunctional design.

1.7.5.2 Scripting IP Simulation

The Intel Quartus Prime software supports the use of scripts to automate simulation

processing in your preferred simulation environment. Use the scripting methodology

that you prefer to control simulation.

Use a version-independent, top-level simulation script to control design, testbench,

and IP core simulation. Because Intel Quartus Prime-generated simulation file names

may change after IP upgrade or regeneration, your top-level simulation script must

"source" the generated setup scripts, rather than using the generated setup scripts

directly. Follow these steps to generate or regenerate combined simulator setup

scripts:

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

48

Figure 21.

Incorporating Generated Simulator Setup Scripts into a Top-Level Simulation

Script

Top-Level Simulation Script

Specify project-specific settings:

  TOP_LEVEL_NAME

 

 
 
 

Source the Combined IP Setup Simulator Script

(e.g., source msim_setup.tcl)

Elaborate
Simulate

Individual IP

Simulation Scripts

Combined IP

Simulator Script

(Includes Templates)

Click “Generate Simulator Script for IP”

Additional compile and elaboration options

Compile design files:

Use generated scripts to compile device libraries
and IP files
Compile your design and testbench files

Add optional QSYS_SIMDIR variable

1. Click Project 

➤

 Upgrade IP Components 

➤

 Generate Simulator Script for IP

(or run the 

ip-setup-simulation

 utility) to generate or regenerate a combined

simulator setup script for all IP for each simulator.

2. Use the templates in the generated script to source the combined script in your

top-level simulation script. Each simulator's combined script file contains a

rudimentary template that you adapt for integration of the setup script into a top-

level simulation script.
This technique eliminates manual update of simulation scripts if you modify or

upgrade the IP variation.

1.7.5.2.1 Generating a Combined Simulator Setup Script

Run the Generate Simulator Setup Script for IP command to generate a combined

simulator setup script.

Source this combined script from a top-level simulation script. Click Tools 

➤

Generate Simulator Setup Script for IP (or use of the 

ip-setup-simulation

utility at the command-line) to generate or update the combined scripts, after any of

the following occur:
•

IP core initial generation or regeneration with new parameters

•

Intel Quartus Prime software version upgrade

•

IP core version upgrade

To generate a combined simulator setup script for all project IP cores for each

simulator:

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

49

1. Generate, regenerate, or upgrade one or more IP core. Refer to Generating IP

Cores or Upgrading IP Cores.

2. Click Tools 

➤

 Generate Simulator Setup Script for IP (or run the 

ip-setup-

simulation

 utility). Specify the Output Directory and library compilation

options. Click OK to generate the file. By default, the files generate into the 

/

<project directory>/<simulator>/

 directory using relative paths.

3. To incorporate the generated simulator setup script into your top-level simulation

script, refer to the template section in the generated simulator setup script as a

guide to creating a top-level script:
a. Copy the specified template sections from the simulator-specific generated

scripts and paste them into a new top-level file.

b. Remove the comments at the beginning of each line from the copied template

sections.

c. Specify the customizations you require to match your design simulation

requirements, for example:
•

Specify the 

TOP_LEVEL_NAME

 variable to the design’s simulation top-level

file. The top-level entity of your simulation is often a testbench that

instantiates your design. Then, your design instantiates IP cores or
Platform Designer systems. Set the value of 

TOP_LEVEL_NAME

 to the top-

level entity.

•

If necessary, set the 

QSYS_SIMDIR

 variable to point to the location of the

generated IP simulation files.

•

Compile the top-level HDL file (for example, a test program) and all other

files in the design.

•

Specify any other changes, such as using the 

grep

 command-line utility to

search a transcript file for error signatures, or e-mail a report.

4. Re-run Tools 

➤

 Generate Simulator Setup Script for IP (or 

ip-setup-

simulation

) after regeneration of an IP variation.

Table 10.

Simulation Script Utilities

Utility

Syntax

ip-setup-simulation

 generates a

combined, version-independent simulation

script for all Intel FPGA IP cores in your project.

The command also automates regeneration of

the script after upgrading software or IP
versions. Use the 

compile-to-work

 option to

compile all simulation files into a single work

library if your simulation environment requires.
Use the 

--use-relative-paths

 option to

use relative paths whenever possible.

ip-setup-simulation
 --quartus-project=

<my proj>

 --output-directory=

<my_dir>

 --use-relative-paths
 --compile-to-work

--use-relative-paths

 and 

--compile-to-work

 are optional. For

command-line help listing all options for these executables, type:

<utility name>

 --help.

ip-make-simscript

 generates a combined

simulation script for all IP cores that you

specify on the command line. Specify one or
more 

.spd

 files and an output directory in the

command. Running the script compiles IP

simulation models into various simulation

libraries.

ip-make-simscript 
 --spd=

<ipA.spd,ipB.spd>

 

 --output-directory=

<directory>

The following sections provide step-by-step instructions for sourcing each simulator

setup script in your top-level simulation script.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

50

Sourcing Aldec* Simulator Setup Scripts

Follow these steps to incorporate the generated Aldec simulation scripts into a top-

level project simulation script.
1. The generated simulation script contains the following template lines. Cut and

paste these lines into a new file. For example, 

sim_top.tcl

.

# # Start of template 
# # If the copied and modified template file is "aldec.do", run it as: 
# # vsim -c -do aldec.do 
# # 
# # Source the generated sim script 
# source rivierapro_setup.tcl 
# # Compile eda/sim_lib contents first 
# dev_com 
# # Override the top-level name (so that elab is useful) 
# set TOP_LEVEL_NAME top 
# # Compile the standalone IP. 
# com 
# # Compile the top-level 
# vlog -sv2k5 ../../top.sv 
# # Elaborate the design. 
# elab 
# # Run the simulation 
# run 
# # Report success to the shell 
# exit -code 0 
# # End of template

2. Delete the first two characters of each line (comment and space):

# Start of template 
# If the copied and modified template file is "aldec.do", run it as: 
# vsim -c -do aldec.do 
# 
# Source the generated sim script source rivierapro_setup.tcl 
# Compile eda/sim_lib contents first dev_com 
# Override the top-level name (so that elab is useful) 
set TOP_LEVEL_NAME top 
# Compile the standalone IP. 
com 
# Compile the top-level vlog -sv2k5 ../../top.sv 
# Elaborate the design. 
elab 
# Run the simulation 
run 
# Report success to the shell 
exit -code 0
# End of template

3. Modify the 

TOP_LEVEL_NAME

 and compilation step appropriately, depending on

the simulation’s top-level file. For example:

set TOP_LEVEL_NAME sim_top
 vlog –sv2k5 ../../sim_top.sv

4. If necessary, add the 

QSYS_SIMDIR

 variable to point to the location of the

generated IP simulation files. Specify any other changes that you require to match

your design simulation requirements. The scripts offer variables to set compilation

or simulation options. Refer to the generated script for details.

5. Run the new top-level script from the generated simulation directory:

vsim –c –do <path to sim_top>

.tcl

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

51

Sourcing Cadence* Simulator Setup Scripts

Follow these steps to incorporate the generated Cadence IP simulation scripts into a

top-level project simulation script.
1. The generated simulation script contains the following template lines. Cut and

paste these lines into a new file. For example, 

ncsim.sh

.

# # Start of template 
# # If the copied and modified template file is "ncsim.sh", run it as: 
# # ./ncsim.sh 
# # 
# # Do the file copy, dev_com and com steps 
# source ncsim_setup.sh \ 
# SKIP_ELAB=1 \ 
# SKIP_SIM=1 
# 
# # Compile the top level module 
# ncvlog -sv "$QSYS_SIMDIR/../top.sv" 
# 
# # Do the elaboration and sim steps 
# # Override the top-level name 
# # Override the sim options, so the simulation 
# # runs forever (until $finish()). 
# source ncsim_setup.sh \
# SKIP_FILE_COPY=1 \ 
# SKIP_DEV_COM=1 \ 
# SKIP_COM=1 \ 
# TOP_LEVEL_NAME=top \ 
# USER_DEFINED_SIM_OPTIONS="" 
# # End of template

2. Delete the first two characters of each line (comment and space):

# Start of template 
# If the copied and modified template file is "ncsim.sh", run it as: 
# ./ncsim.sh 
# 
# Do the file copy, dev_com and com steps 
source ncsim_setup.sh \ 
SKIP_ELAB=1 \ 
SKIP_SIM=1 
# Compile the top level module 
ncvlog -sv "$QSYS_SIMDIR/../top.sv" 
# Do the elaboration and sim steps 
# Override the top-level name 
# Override the sim options, so the simulation 
# runs forever (until $finish()). 
source ncsim_setup.sh \
SKIP_FILE_COPY=1 \ 
SKIP_DEV_COM=1 \ 
SKIP_COM=1 \ 

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

52

TOP_LEVEL_NAME=top \ 
USER_DEFINED_SIM_OPTIONS="" 
# End of template

3. Modify the 

TOP_LEVEL_NAME

 and compilation step appropriately, depending on

the simulation’s top-level file. For example:

TOP_LEVEL_NAME=sim_top \
 ncvlog -sv "$QSYS_SIMDIR/../top.sv"

4. If necessary, add the 

QSYS_SIMDIR

 variable to point to the location of the

generated IP simulation files. Specify any other changes that you require to match

your design simulation requirements. The scripts offer variables to set compilation

or simulation options. Refer to the generated script for details.

5. Run the resulting top-level script from the generated simulation directory by

specifying the path to 

ncsim.sh

.

Sourcing ModelSim* Simulator Setup Scripts

Follow these steps to incorporate the generated ModelSim IP simulation scripts into a

top-level project simulation script.
1. The generated simulation script contains the following template lines. Cut and

paste these lines into a new file. For example, 

sim_top.tcl

.

# # Start of template
# # If the copied and modified template file is "mentor.do", run it
# # as: vsim -c -do mentor.do 
# # 
# # Source the generated sim script
# source msim_setup.tcl 
# # Compile eda/sim_lib contents first 
# dev_com 
# # Override the top-level name (so that elab is useful) 
# set TOP_LEVEL_NAME top 
# # Compile the standalone IP. 
# com 
# # Compile the top-level 
# vlog -sv ../../top.sv 
# # Elaborate the design. 
# elab 
# # Run the simulation 
# run -a 
# # Report success to the shell
# exit -code 0 
# # End of template

2. Delete the first two characters of each line (comment and space):

# Start of template
# If the copied and modified template file is "mentor.do", run it
# as: vsim -c -do mentor.do 
# 
# Source the generated sim script source msim_setup.tcl 
# Compile eda/sim_lib contents first 
dev_com 
# Override the top-level name (so that elab is useful) 
set TOP_LEVEL_NAME top 
# Compile the standalone IP. 
com 
# Compile the top-level vlog -sv ../../top.sv 
# Elaborate the design. 
elab 
# Run the simulation 
run -a 

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

53

# Report success to the shell
exit -code 0 
# End of template

3. Modify the 

TOP_LEVEL_NAME

 and compilation step appropriately, depending on

the simulation’s top-level file. For example:

set TOP_LEVEL_NAME sim_top vlog -sv ../../sim_top.sv

4. If necessary, add the 

QSYS_SIMDIR

 variable to point to the location of the

generated IP simulation files. Specify any other changes required to match your

design simulation requirements. The scripts offer variables to set compilation or

simulation options. Refer to the generated script for details.

5. Run the resulting top-level script from the generated simulation directory:

vsim –c –do <path to sim_top>.tcl

Sourcing VCS* Simulator Setup Scripts

Follow these steps to incorporate the generated Synopsys VCS simulation scripts into

a top-level project simulation script.
1. The generated simulation script contains these template lines. Cut and paste the

lines preceding the “helper file” into a new executable file. For example,

synopsys_vcs.f

.

# # Start of template 
# # If the copied and modified template file is "vcs_sim.sh", run it 
# # as: ./vcs_sim.sh 
# # 
# # Override the top-level name 
# # specify a command file containing elaboration options 
# # (system verilog extension, and compile the top-level). 
# # Override the sim options, so the simulation 
# # runs forever (until $finish()). 
# source vcs_setup.sh \ 
# TOP_LEVEL_NAME=top \ 
# USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" \ 
# USER_DEFINED_SIM_OPTIONS="" 
# 
# # helper file: synopsys_vcs.f 
# +systemverilogext+.sv 
# ../../../top.sv 
# # End of template

2. Delete the first two characters of each line (comment and space) for the 

vcs.sh

file, as shown below:

# Start of template 
# If the copied and modified template file is "vcs_sim.sh", run it 
# as: ./vcs_sim.sh 
# 
# Override the top-level name 
# specify a command file containing elaboration options 
# (system verilog extension, and compile the top-level). 
# Override the sim options, so the simulation 
# runs forever (until $finish()). 
source vcs_setup.sh \ 

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

54

TOP_LEVEL_NAME=top \ 
USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" \
USER_DEFINED_SIM_OPTIONS=""

3. Delete the first two characters of each line (comment and space) for the

synopsys_vcs.f

 file, as shown below:

# helper file: synopsys_vcs.f 
 +systemverilogext+.sv 
 ../../../top.sv
# End of template

4. Modify the 

TOP_LEVEL_NAME

 and compilation step appropriately, depending on

the simulation’s top-level file. For example:

TOP_LEVEL_NAME=sim_top \

5. If necessary, add the 

QSYS_SIMDIR

 variable to point to the location of the

generated IP simulation files. Specify any other changes required to match your

design simulation requirements. The scripts offer variables to set compilation or

simulation options. Refer to the generated script for details.

6. Run the resulting top-level script from the generated simulation directory by

specifying the path to 

vcs_sim.sh

.

Sourcing VCS* MX Simulator Setup Scripts

Follow these steps to incorporate the generated Synopsys VCS MX simulation scripts

for use in top-level project simulation scripts.
1. The generated simulation script contains these template lines. Cut and paste the

lines preceding the “helper file” into a new executable file. For example,

vcsmx.sh

.

# # Start of template 
# # If the copied and modified template file is "vcsmx_sim.sh", run 
# # it as: ./vcsmx_sim.sh 
# # 
# # Do the file copy, dev_com and com steps 
# source vcsmx_setup.sh \ 
# SKIP_ELAB=1 \
      
# SKIP_SIM=1 
# 
# # Compile the top level module vlogan +v2k
     +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv" 
  
# # Do the elaboration and sim steps 
# # Override the top-level name 
# # Override the sim options, so the simulation runs 
# # forever (until $finish()). 
# source vcsmx_setup.sh \ 
# SKIP_FILE_COPY=1 \ 
# SKIP_DEV_COM=1 \ 
# SKIP_COM=1 \ 
# TOP_LEVEL_NAME="'-top top'" \ 
# USER_DEFINED_SIM_OPTIONS="" 
# # End of template

2. Delete the first two characters of each line (comment and space), as shown

below:

# Start of template 
# If the copied and modified template file is "vcsmx_sim.sh", run 
# it as: ./vcsmx_sim.sh 
# 

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

55

# Do the file copy, dev_com and com steps 
source vcsmx_setup.sh \ 
SKIP_ELAB=1 \
SKIP_SIM=1 
  
# Compile the top level module 
vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv" 
   
# Do the elaboration and sim steps 
# Override the top-level name 
# Override the sim options, so the simulation runs 
# forever (until $finish()). 
source vcsmx_setup.sh \ 
SKIP_FILE_COPY=1 \ 
SKIP_DEV_COM=1 \ 
SKIP_COM=1 \ 
TOP_LEVEL_NAME="'-top top'" \ 
USER_DEFINED_SIM_OPTIONS="" 
# End of template

3. Modify the 

TOP_LEVEL_NAME

 and compilation step appropriately, depending on

the simulation’s top-level file. For example:

TOP_LEVEL_NAME=”-top sim_top’” \

4. Make the appropriate changes to the compilation of the your top-level file, for

example:

vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../sim_top.sv"

5. If necessary, add the 

QSYS_SIMDIR

 variable to point to the location of the

generated IP simulation files. Specify any other changes required to match your

design simulation requirements. The scripts offer variables to set compilation or

simulation options. Refer to the generated script for details.

6. Run the resulting top-level script from the generated simulation directory by

specifying the path to 

vcsmx_sim.sh

.

1.7.5.3 Using NativeLink Simulation (Intel Quartus Prime Standard Edition)

The NativeLink feature integrates your EDA simulator with the Intel Quartus Prime

Standard Edition software by automating the following:
•

Generation of simulator-specific files and simulation scripts.

•

Compilation of simulation libraries.

•

Launches your simulator automatically following Intel Quartus Prime Analysis &

Elaboration, Analysis & Synthesis, or after a full compilation.

Note: 

The Intel Quartus Prime Pro Edition does not support NativeLink simulation. If you use

NativeLink for Intel Arria 10 devices in the Intel Quartus Prime Standard Edition, you
must add the 

.qsys

 file generated for the IP or Platform Designer (Standard) system

to your Intel Quartus Prime project. If you use NativeLink for any other supported
device family, you must add the 

.qip

 and 

.sip

 files to your project.

1.7.5.3.1 Setting Up NativeLink Simulation (Intel Quartus Prime Standard Edition)

Before running NativeLink simulation, specify settings for your simulator in the Intel

Quartus Prime software.

To specify NativeLink settings in the Intel Quartus Prime Standard Edition software,

follow these steps:

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

56

1. Open an Intel Quartus Prime Standard Edition project.
2. Click Tools > Options and specify the location of your simulator executable file.

Table 11.

Execution Paths for EDA Simulators

Simulator

Path

Mentor Graphics 

ModelSim-AE

<drive letter>:\<simulator install path>\win32aloem

 (Windows)

/<simulator install path>/bin

 (Linux)

Mentor Graphics ModelSim

Mentor Graphics QuestaSim

<drive letter>:\<simulator install path>\win32

 (Windows)

<simulator install path>/bin

 (Linux)

Synopsys VCS/VCS MX

<simulator install path>/bin

 (Linux)

Cadence Incisive Enterprise

<simulator install path>/tools/bin

 (Linux)

Aldec Active-HDL

Aldec Riviera-PRO

<drive letter>:\<simulator install path>\bin

 (Windows)

<simulator install path>/bin

 (Linux)

3. Click Assignments 

➤

 Settings and specify options on the Simulation page and

the More NativeLink Settings dialog box. Specify default options for simulation

library compilation, netlist and tool command script generation, and for launching

RTL or gate-level simulation automatically following compilation.

4. If your design includes a testbench, turn on Compile test bench. Click Test

Benches to specify options for each testbench. Alternatively, turn on Use script

to compile testbench and specify the script file.

5. To use a script to setup a simulation, turn on Use script to setup simulation.

1.7.5.3.2 Generating IP Functional Simulation Models (Intel Quartus Prime Standard

Edition)

Intel provides IP functional simulation models for some Intel FPGA IP supporting 40nm

FPGA devices.

To generate IP functional simulation models:
1. Turn on the Generate Simulation Model option when parameterizing the IP

core.

2. When you simulate your design, compile only the 

.vo

 or 

.vho

 for these IP cores

in your simulator. Do not compile the corresponding HDL file. The encrypted HDL

file supports synthesis by only the Intel Quartus Prime software.
Note: •

Intel FPGA IP cores that do not require IP functional simulation models

for simulation, do not provide the Generate Simulation Model option

in the IP core parameter editor.

•

Many recently released Intel FPGA IP cores support RTL simulation using

IEEE Verilog HDL encryption. IEEE encrypted models are significantly

faster than IP functional simulation models. Simulate the models in both

Verilog HDL and VHDL designs.

Related Links
AN 343: Intel FPGA IP Evaluation Mode of AMPP IP

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

57

1.7.6 Synthesizing IP Cores in Other EDA Tools

Optionally, use another supported EDA tool to synthesize a design that includes Intel

FPGA IP cores. When you generate the IP core synthesis files for use with third-party

EDA synthesis tools, you can create an area and timing estimation netlist. To enable

generation, turn on Create timing and resource estimates for third-party EDA

synthesis tools when customizing your IP variation.

The area and timing estimation netlist describes the IP core connectivity and

architecture, but does not include details about the true functionality. This information

enables certain third-party synthesis tools to better report area and timing estimates.

In addition, synthesis tools can use the timing information to achieve timing-driven

optimizations and improve the quality of results.

The Intel Quartus Prime software generates the 

<variant name>_syn.v

 netlist file

in Verilog HDL format, regardless of the output file format you specify. If you use this
netlist for synthesis, you must include the IP core wrapper file <variant name>

.v

 or

<variant name> 

.vhd

 in your Intel Quartus Prime project.

1.7.7 Instantiating IP Cores in HDL

Instantiate an IP core directly in your HDL code by calling the IP core name and

declaring the IP core's parameters. This approach is similar to instantiating any other

module, component, or subdesign. When instantiating an IP core in VHDL, you must

include the associated libraries.

1.7.7.1 Example Top-Level Verilog HDL Module

Verilog HDL ALTFP_MULT in Top-Level Module with One Input Connected to Multiplexer.

module MF_top (a, b, sel, datab, clock, result);
       input [31:0] a, b, datab;
       input clock, sel;
       output [31:0] result;
       wire [31:0] wire_dataa;    
    
       assign wire_dataa = (sel)? a : b;  
       altfp_mult inst1 
(.dataa(wire_dataa), .datab(datab), .clock(clock), .result(result));
    
       defparam 
               inst1.pipeline = 11,
               inst1.width_exp = 8,
               inst1.width_man = 23,
               inst1.exception_handling = "no";                
endmodule

1.7.7.2 Example Top-Level VHDL Module

VHDL ALTFP_MULT in Top-Level Module with One Input Connected to Multiplexer.

library ieee;
use ieee.std_logic_1164.all; 
library altera_mf;
use altera_mf.altera_mf_components.all; 

entity MF_top is
        port (clock, sel  : in  std_logic;                
              a, b, datab : in  std_logic_vector(31 downto 0);            
              result      : out std_logic_vector(31 downto 0));

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

58

end entity;

architecture arch_MF_top of MF_top is
signal wire_dataa : std_logic_vector(31 downto 0);
begin

wire_dataa <= a when (sel = '1') else b;
    
inst1 : altfp_mult 
        generic map    (
                   pipeline => 11,
                   width_exp => 8,
                   width_man => 23,        
                   exception_handling => "no")        
        port map (
                   dataa => wire_dataa,
                   datab => datab,
                   clock => clock,
                   result => result);    
end arch_MF_top;

1.8 Integrating Other EDA Tools

Optionally integrate supported EDA design entry, synthesis, simulation, physical

synthesis, and formal verification tools into the Intel Quartus Prime design flow. The

Intel Quartus Prime software supports netlist files from other EDA design entry and

synthesis tools. The Intel Quartus Prime software optionally generates various files for

use in other EDA tools.

The Intel Quartus Prime software manages EDA tool files and provides the following

integration capabilities:
•

Automatically generate files for synthesis and simulation and automatically launch

other EDA tools (Assignments > Settings > EDA Tool Settings > NativeLink

Settings ). The Intel Quartus Prime Pro Edition software does not support

NativeLink.

•

Compile all RTL and gate-level simulation model libraries for your device,

simulator, and design language automatically (Tools > Launch Simulation

Library Compiler).

•

Include files generated by other EDA design entry or synthesis tools in your

project as synthesized design files (Project > Add/Remove File from Project) .

•

Automatically generate optional files for board-level verification (Assignments >

Settings > EDA Tool Settings).

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

59

Figure 22.

EDA Tool Settings

1.9 Managing Team-based Projects

The Intel Quartus Prime software supports multiple designers, design iterations, and

platforms. Use the following techniques to preserve and track project changes in a

team-based environment. These techniques may also be helpful for individual

designers.

Related Links

•

Using External Revision Control

 on page 64

•

Migrating Projects Across Operating Systems

 on page 65

1.9.1 Preserving Compilation Results

The Intel Quartus Prime software allows you to transfer your compiled databases from

one version of the software to a newer version of the software.

The Intel Quartus Prime software maintains a database of compilation results for each

project revision. The database file stores the compilation results. Do not edit these

files directly. However, you can use the database files in the following ways:
•

Preserve compilation results for migration to a new version of the Intel Quartus

Prime software. Export a post-synthesis or post-fit, version-compatible database

(Project > Export Database), and then import it into a newer version of the

Intel Quartus Prime software (Project > Import Database), or into another

project.

•

Optimize and lock down the compilation results for individual blocks. Export the

post-synthesis or post-fit netlist as a Intel Quartus Prime Exported Partition File
(

.qxp

) (Project > Export Design Partition). You can then import the partition

as a new project design file.

•

Purge the content of the project database (Project > Clean Project) to remove

unwanted previous compilation results at any time.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

60

1.9.2 Factors Affecting Compilation Results

Various changes to project settings, hardware, or software can impact compilation

results.

•

Project Files—project settings (

.qsf

, 

quartus2.ini

), design files, and timing

constraints (

.sdc

). Any setting that changes the number of processors during

compilation can impact compilation results.

•

Hardware—CPU architecture, not including hard disk or memory size differences.

Windows XP x32 results are not identical to Windows XP x64 results. Linux x86

results is not identical to Linux x86_64.

•

Intel Quartus Prime Software Version—including build number and installed

interim updates. Click Help > About to obtain this information.

•

Operating System—Windows or Linux operating system, excluding version

updates. For example, Windows XP, Windows Vista, and Windows 7 results are

identical. Similarly, Linux RHEL, CentOS 4, and CentOS 5 results are identical.

Related Links

•

Design Planning for Partial Reconfiguration

 on page 154

•

Power-Up Level

 on page 979

1.9.3 Migrating Compilation Results Across Intel Quartus Prime Software

Versions

View basic information about your project in the Project Navigator, Report panel, and

Messages window.

To preserve compilation results for migration to a newer version of the Intel Quartus

Prime software, export a version-compatible database file, and then import it into the

later version of the Intel Quartus Prime software.

1.9.3.1 Exporting the Results Database

Follow these steps to save the compilation results in a version-compatible format for

import to a different version of the Intel Quartus Prime software.

1. Open the project for exporting the compilation results in the Intel Quartus Prime

software.

2. Generate the project database and netlist with one of the following:

•

Click Processing 

➤

 Start 

➤

 Start Analysis & Synthesis to generate a post-

synthesis netlist.

•

Click Processing 

➤

 Start Compilation to generate a post-fit netlist.

3. Click Project > Export Database and specify the Export directory.

Note: 

You can turn on Assignments > Settings > Compilation Process Settings >

Export version-compatible database if you want to always export the database

following compilation.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

61

Figure 23.

Intel Quartus Prime Version-Compatible Database Structure

1.9.3.2 Importing the Results Database

Follow these steps to import the compilation results from a previous version of the

Intel Quartus Prime software to another version of the software.

1. In a newer version of the Intel Quartus Prime software, click New Project

Wizard and create a new project with the same top-level design entity name as

the database.

2. Click Project > Import Database and select the 

<project directory>/

export_db/

 exported database directory. The Intel Quartus Prime software

opens the compiled project and displays compilation results.
The Timing analysis mode option is only available for Intel Arria 10 designs. The

option disables legality checks for certain configuration rules that may have

changed from prior versions of the Intel Quartus Prime software. Use this option

only if you cannot successfully import your design without it. After you have

imported a design in timing analysis mode, you cannot use it to generate

programming files.

1.9.3.3 Cleaning the Project Database

Follow these steps to clean the project database and remove all prior compilation

results.

1. Click Project > Clean Project.
2. Select All revisions to remove the databases for all revisions of the current

project, or specify a Revision name to remove only that revision’s database.

3. Click OK. A message indicates when the database is clean.

1.9.4 Archiving Projects

Optionally save the elements of a project in a single, compressed Intel Quartus Prime
Archive File (

.qar

) by clicking Project > Archive Project.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

62

The 

.qar

 preserves logic design, project, and settings files required to restore the

project.

Use this technique to share projects between designers, or to transfer your project to

a new version of the Intel Quartus Prime software, or to Intel support. Optionally add

compilation results, Platform Designer (Standard) system files, and third-party EDA

tool files to the archive. If you restore the archive in a different version of the Intel
Quartus Prime software, you must include the original 

.qdf

 in the archive to preserve

original compilation results.

1.9.4.1 Manually Adding Files To Archives

Follow these steps to add files to an archive manually.

1. Click Project > Archive Project and specify the archive file name.
2. Click Advanced.
3. Select the File set for archive or select Custom. Turn on File subsets for

archive.

4. Click Add and select Platform Designer (Standard) system or EDA tool files. Click

OK.

5. Click Archive.

1.9.4.2 Archiving Compilation Results

Optionally include compilation results in a project archive to avoid recompilation and

preserve original results in the restored project. To archive compilation results, export

the post-synthesis or post-fit version compatible database and include this file in the

archive.

1. Export the project database.
2. Click Project > Archive Project and specify the archive file name.
3. Click Advanced.
4. Under File subsets, turn on Version-compatible database files and click OK.
5. Click Archive.

To restore an archive containing a version-compatible database, follow these steps:
1. Click Project > Restore Archived Project.
2. Select the archive name and destination folder and click OK.
3. After restoring the archived project, click Project > Import Database and

import the version-compatible database.

Related Links
Exporting the Results Database

 on page 61

1.9.4.3 Archiving Projects for Service Requests

When archiving projects for a service request, include all needed file types for proper

debugging by customer support.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

63

To identify and include appropriate archive files for an Intel service request:
1. Click Project > Archive Project and specify the archive file name.
2. Click Advanced.
3. In File set, select Service request to include files for Intel Support.

•

Project source and setting files
(

.v

, 

.vhd

, 

.vqm

, 

.qsf

, 

.sdc

, 

.qip

, 

.qpf

,

 .cmp

)

•

Automatically detected source files (various)

•

Programming output files (

.jdi

, 

.sof

, 

.pof

)

•

Report files (

.rpt

, 

.pin

,

 .summary

, 

.smsg

)

•

Platform Designer system and IP files (

.qsys

, 

.qip

)

4. Click OK, and then click Archive.

Figure 24.

Archiving Project for Service Request

1.9.5 Using External Revision Control

Your project may involve different team members with distributed responsibilities,

such as sub-module design, device and system integration, simulation, and timing

closure. In such cases, it may be useful to track and protect file revisions in an

external revision control system.

While Intel Quartus Prime project revisions preserve various project setting and

constraint combinations, external revision control systems can also track and merge

RTL source code, simulation testbenches, and build scripts. External revision control

supports design file version experimentation through branching and merging different

versions of source code from multiple designers. Refer to your external revision

control documentation for setup information.

1.9.5.1 Files to Include In External Revision Control

Include the following project file types in external revision control systems:

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

64

•

Logic design files (

.v

, .

vdh

, 

.bdf

, 

.edf

, 

.vqm

)

•

Timing constraint files (.sdc)

•

Quartus project settings and constraints (

.qdf

, 

.qpf

, 

.qsf

)

•

IP files (

.ip

, 

.v

, 

.sv

, 

.vhd

, 

.qip

, 

.sip

, 

.qsys

)

•

Platform Designer (Standard)-generated files (

.qsys

, 

.ip

, 

.sip

)

•

EDA tool files (

.vo

, 

.vho

 )

Generate or modify these files manually if you use a scripted design flow. If you use

an external source code control system, check-in project files anytime you modify

assignments and settings.

1.9.6 Migrating Projects Across Operating Systems

Consider the following cross-platform issues when moving your project from one

operating system to another (for example, from Windows to Linux).

1.9.6.1 Migrating Design Files and Libraries

Consider file naming differences when migrating projects across operating systems.

•

Use appropriate case for your platform in file path references.

•

Use a character set common to both platforms.

•

Do not change the forward-slash (

/)

 and back-slash (

\)

 path separators in

the 

.qsf

. The Intel Quartus Prime software automatically changes all back-slash

(

\)

 path separators to forward-slashes (

/

 

)

in the 

.qsf

.

•

Observe the target platform’s file name length limit.

•

Use underscore instead of spaces in file and directory names.

•

Change library absolute path references to relative paths in the 

.qsf

.

•

Ensure that any external project library exists in the new platform’s file system.

•

Specify file and directory paths as relative to the project directory. For example,
for a project titled 

foo_design

, specify the source files as: 

top.v

,

foo_folder /foo1.v

, 

foo_folder /foo2.v

, and 

foo_folder/

bar_folder/bar1.vhdl

.

•

Ensure that all the subdirectories are in the same hierarchical structure and

relative path as in the original platform.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

65

Figure 25.

All Inclusive Project Directory Structure

1.9.6.1.1 Use Relative Paths

Express file paths using relative path notation (.. /).

For example, in the directory structure shown you can specify top.v as ../source/

top.v and foo1.v as ../source/foo_folder/foo1.v.

Figure 26.

Intel Quartus Prime Project Directory Separate from Design Files

1.9.6.2 Design Library Migration Guidelines

The following guidelines apply to library migration across computing platforms:

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

66

1. The project directory takes precedence over the project libraries.
2. For Linux, the Intel Quartus Prime software creates the file in the altera.quartus

directory under the <home> directory.

3. All library files are relative to the libraries. For example, if you specify the

user_lib1

 directory as a project library and you want to add the 

/user_lib1/

foo1.v

 file to the library, you can specify the 

foo1.v

 file in the 

.qsf

 as 

foo1.v

.

The Intel Quartus Prime software includes files in specified libraries.

4. If the directory is outside of the project directory, an absolute path is created by

default. Change the absolute path to a relative path before migration.

5. When copying projects that include libraries, you must either copy your project

library files along with the project directory or ensure that your project library files

exist in the target platform.
•

On Windows, the Intel Quartus Prime software searches for the

quartus2.ini

 file in the following directories and order:

•

USERPROFILE, for example, 

C:\Documents and Settings\<user name>

•

Directory specified by the TMP environmental variable

•

Directory specified by the TEMP environmental variable

•

Root directory, for example, C:\

1.10 Scripting API

Optionally use command-line executables or scripts to execute project commands,

rather than using the GUI. The following commands are available for scripting project

management.

1.10.1 Scripting Project Settings

Optionally use a Tcl script to specify settings and constraints, rather than using the

GUI. This technique can be helpful if you have many settings and wish to track them

in a single file or spreadsheet for iterative comparison. The .qsf supports only a

limited subset of Tcl commands. Therefore, pass settings and constraints using a Tcl

script:

1. Create a text file with the extension.tcl that contains your assignments in Tcl

format.

2. Source the Tcl script file by adding the following line to the .qsf:

set_global_assignment -name SOURCE_TCL_SCR IPT_FILE <file

name>

.

1.10.2 Project Revision Commands

Use the following commands for scripting project revisions.

Create Revision Command

 on page 68

Set Current Revision Command

 on page 68

Get Project Revisions Command

 on page 68

Delete Revision Command

 on page 68

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

67

1.10.2.1 Create Revision Command

create_revision <name> -based_on <revision_name> -copy_results -set_current
                     

Option

Description

based_on

 (optional)

Specifies the revision name on which the new revision bases its settings.

copy_results

Copies the results from the "based_on" revision.

set_current

 (optional)

Sets the new revision as the current revision.

1.10.2.2 Set Current Revision Command

The 

-force

 option enables you to open the revision that you specify under revision

name and overwrite the compilation database if the database version is incompatible.

set_current_revision -force <revision name>

1.10.2.3 Get Project Revisions Command

get_project_revisions <project_name>

1.10.2.4 Delete Revision Command

 delete_revision <revision name>

1.10.3 Project Archive Commands

Optionally use Tcl commands and the 

quartus_sh

 executable to create and manage

archives of a Quartus project.

1.10.3.1 Creating a Project Archive

Use the following command to create a Intel Quartus Prime archive:

project_archive <name>.qar

You can specify the following other options:
•

-all_revisions

 - Includes all revisions of the current project in the archive.

•

-auto_common_directory

 - Preserves original project directory structure in

archive

•

-common_directory /<name>

 - Preserves original project directory structure in

specified subdirectory

•

-include_libraries

 - Includes libraries in archive

•

-include_outputs

 - Includes output files in archive

•

-use_file_set <file_set>

 - Includes specified fileset in archive

•

-version_compatible_database

 - Includes version-compatible database files

in archive

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

68

Note: 

Version-compatible databases are not available for some device families. If you

require the database files to reproduce the compilation results in the same Intel
Quartus Prime software version, use the 

-use_file_set full_db

 option to archive

the complete database.

1.10.3.2 Restoring an Archived Project

Use the following Tcl command to restore a Quartus project:

project_restore <name>.qar -destination restored -overwrite 
        

This example restores to a destination directory named "restored".

1.10.4 Project Database Commands

Use the following commands for managing Quartus project databases:

Import and Export Version-Compatible Databases

 on page 69

Import and Export Version-Compatible Databases from a Flow Package

 on page 69

Generate Version-Compatible Database After Compilation

 on page 69

quartus_cdb and quartus_sh Executables to Manage Version-Compatible Databases

 on

page 70

1.10.4.1 Import and Export Version-Compatible Databases

Use the following commands to import or export a version-compatible database:
•

import_database <directory>

•

export_database <directory>

1.10.4.2 Import and Export Version-Compatible Databases from a Flow Package

The following are Tcl commands from the 

flow

 package to import or export version-

compatible databases. If you use the 

flow

 package, you must specify the database

directory variable name. 

flow

 and 

database_manager

 packages contain commands

to manage version-compatible databases.
•

set_global_assignment -name VER_COMPATIBLE_DB_DIR <directory>

•

execute_flow –flow export_database

•

execute_flow –flow import_database

1.10.4.3 Generate Version-Compatible Database After Compilation

Use the following commands to generate a version-compatible database after

compilation:
•

set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB ON

•

set_global_assignment-name VER_COMPATIBLE_DB_DIR <directory>

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

69

1.10.4.4 quartus_cdb and quartus_sh Executables to Manage Version-Compatible

Databases

Use the following commands to manage version-compatible databases:
•

quartus_cdb <project> -c <revision> --

export_database=<directory>

•

quartus_cdb <project> -c <revision> --

import_database=<directory>

•

quartus_sh –flow export_database <project> -c \ <revision>

•

quartus_sh –flow import_database <project> -c \ <revision>

1.10.5 Project Library Commands

Use the following commands to script project library changes.

Specify Project Libraries With SEARCH_PATH Assignment

 on page 70

Report Specified Project Libraries Commands

 on page 70

1.10.5.1 Specify Project Libraries With SEARCH_PATH Assignment

In Tcl, use commands in the 

::

 

quartus

 

::project

 package to specify project

libraries, and the 

set_global_assignment

 command.

Use the following commands to script project library changes:
•

set_global_assignment -name SEARCH_PATH "../other_dir/

library1"

•

set_global_assignment -name SEARCH_PATH "../other_dir/

library2"

•

set_global_assignment -name SEARCH_PATH "../other_dir/

library3"

1.10.5.2 Report Specified Project Libraries Commands

To report any project libraries specified for a project and any global libraries specified

for the current installation of the Quartus software, use the

get_global_assignment

 and 

get_user_option

 Tcl commands.

Use the following commands to report specified project libraries:
•

get_global_assignment -name SEARCH_PATH

•

get_user_option -name SEARCH_PATH

1.11 Document Revision History

This document has the following revision history.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

70

Table 12.

Document Revision History

Date

Version

Changes

2017.11.06

17.1.0

• Revised product branding for Intel standards.
• Changed instances of Qsys to Platform Designer (Standard)
• Revised topics on Intel FPGA IP Evaluation Mode (formerly

OpenCore).

• Removed 

-compatible

 attribute from 

export_design

 command

content.

• Updated IP Core Upgrade Status table with new icons, and added

row for IP Component Outdated status.

2017.05.08

17.0.0

• Added topic on Back-Annotate Assignments command.

2016.10.31

16.1.0

• Updated screenshots.

2016.05.03

16.0.0

Removed statements about serial equivalence when using multiple

processors.

2016.02.09

15.1.1

• Clarified instructions for Generating a Combined Simulator Setup

Script.

• Clarified location of Save project output files in specified

directory option.

2015.11.02

15.1.0

Changed instances of Quartus II to Intel Quartus Prime.

2015.05.04

15.0.0

• Added description of design templates feature.
• Updated screenshot for DSE II GUI.
• Added qsys_script IP core instantiation information.
• Described changes to generating and processing of instance and

entity names.

• Added description of upgrading IP cores at the command line.
• Updated procedures for upgrading and migrating IP cores.
• Gate level timing simulation supported only for Cyclone IV and

Stratix IV devices.

2014.12.15

14.1.0

• Updated content for DSE II GUI and optimizations.
• Added information about new Assignments 

➤

 Settings 

➤

 IP

Settings that control frequency of synthesis file regeneration and

automatic addtion of IP files to the project.

2014.08.18

14.0a10.0

• Added information about specifying parameters for IP cores

targeting Arria 10 devices.

• Added information about the latest IP output for version 14.0a10

targeting Arria 10 devices.

• Added information about individual migration of IP cores to the

latest devices.

• Added information about editing existing IP variations.

2014.06.30

14.0.0

• Replaced MegaWizard Plug-In Manager information with IP Catalog.
• Added standard information about upgrading IP cores.
• Added standard installation and licensing information.
• Removed outdated device support level information. IP core device

support is now available in IP Catalog and parameter editor.

November 2013

13.1.0

• Conversion to DITA format

May 2013

13.0.0

• Overhaul for improved usability and updated information.

continued...   

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

71

Date

Version

Changes

June 2012

12.0.0

• Removed survey link.
• Updated information about 

VERILOG_INCLUDE_FILE

.

November 2011

10.1.1

Template update.

December 2010

10.1.0

• Changed to new document template.
• Removed Figure 4–1, Figure 4–6, Table 4–2.
• Moved “Hiding Messages” to Help.
• Removed references about the 

set_user_option

 command.

• Removed Classic Timing Analyzer references.

Related Links
Documentation Archive

For previous versions of the Intel Quartus Prime Handbook, search the

documentation archives.

1 Managing Intel

®

 Quartus

®

 Prime Projects

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

72

2 Design Planning with the Intel Quartus Prime Software

2.1 Design Planning with the Intel Quartus Prime Software

Platform planning—the early feasibility analysis of physical constraints—is a

fundamental early step in advanced FPGA design. FPGA device densities and

complexities are increasing and designs often involve multiple designers. System

architects must also resolve design issues when integrating design blocks. However,

you can solve potential problems early in the design cycle by following the design

planning considerations in this chapter.

Before reading the design planning guidelines discussed in this chapter, consider your

design priorities. More device features, density, or performance requirements can

increase system cost. Signal integrity and board issues can impact I/O pin locations.

Power, timing performance, and area utilization all affect each other. Compilation time

is affected when optimizing these priorities.

The Intel Quartus Prime software optimizes designs for the best overall results;

however, you can change the settings to better optimize one aspect of your design,

such as power utilization. Certain tools or debugging options can lead to restrictions in

your design flow. Your design priorities help you choose the tools, features, and

methodologies to use for your design.

After you select a device family, to check if additional guidelines are available, refer to

the design guidelines section of the appropriate device documentation.

2.2 Creating Design Specifications

Before you create your design logic or complete your system design, create detailed

design specifications that define the system, specify the I/O interfaces for the FPGA,

identify the different clock domains, and include a block diagram of basic design

functions.

In addition, creating a test plan helps you to design for verification and ease of

manufacture. For example, you might need to validate interfaces incorporated in your

design. To perform any built-in self-test functions to drive interfaces, you can use a

UART interface with a Nios

®

 II processor inside the FPGA device.

If more than one designer works on your design, you must consider a common design

directory structure or source control system to make design integration easier.

Consider whether you want to standardize on an interface protocol for each design

block.

Related Links

•

Planning for On-Chip Debugging Tools

 on page 83

•

Planning for Hierarchical and Team-Based Design

 on page 85

For more suggestions on team-based designs.

QPS5V1 | 2017.10.06

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus

and  Stratix  words  and  logos  are  trademarks  of  Intel  Corporation  or  its  subsidiaries  in  the  U.S.  and/or  other

countries.  Intel  warrants  performance  of  its  FPGA  and  semiconductor  products  to  current  specifications  in

accordance with Intel's standard warranty, but reserves the right to make changes to any products and services

at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any

information,  product,  or  service  described  herein  except  as  expressly  agreed  to  in  writing  by  Intel.  Intel

customers  are  advised  to  obtain  the  latest  version  of  device  specifications  before  relying  on  any  published

information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2008

Registered

•

Using Platform Designer (Standard) and Standard Interfaces in System Design

 on

page 74

For improved reusability and ease of integration.

2.3 Selecting Intellectual Property Cores

Intel and its third-party intellectual property (IP) partners offer a large selection of

standardized IP cores optimized for Intel devices. The IP you select often affects

system design, especially if the FPGA interfaces with other devices in the system.

Consider which I/O interfaces or other blocks in your system design are implemented

using IP cores, and plan to incorporate these cores in your FPGA design.

The Intel FPGA IP Evaluation Mode, which is available for many IP cores, allows you to

program the FPGA to verify your design in the hardware before you purchase the IP

license. The evaluation supports the following modes:
•

Untethered—the design runs for a limited time.

•

Tethered—the design requires an Intel serial JTAG cable connected between the

JTAG port on your board and a host computer running the Intel Quartus Prime

Programmer for the duration of the hardware evaluation period.

Related Links
Intellectual Property

For descriptions of available IP cores.

2.4 Using Platform Designer (Standard) and Standard Interfaces in

System Design

You can use the Intel Quartus Prime Platform Designer (Standard) system integration

tool to create your design with fast and easy system-level integration. With Platform

Designer (Standard), you can specify system components in a GUI and generate the

required interconnect logic automatically, along with adapters for clock crossing and

width differences.

Because system design tools change the design entry methodology, you must plan to

start developing your design within the tool. Ensure all design blocks use appropriate

standard interfaces from the beginning of the design cycle so that you do not need to

make changes later.

Platform Designer (Standard) components use Avalon

®

 standard interfaces for the

physical connection of components, and you can connect any logical device (either on-

chip or off-chip) that has an Avalon interface. The Avalon Memory-Mapped interface

allows a component to use an address mapped read or write protocol that enables

flexible topologies for connecting master components to any slave components. The

Avalon Streaming interface enables point-to-point connections between streaming

components that send and receive data using a high-speed, unidirectional system

interconnect between source and sink ports.

In addition to enabling the use of a system integration tool such as Platform Designer

(Standard), using standard interfaces ensures compatibility between design blocks

from different design teams or vendors. Standard interfaces simplify the interface

logic to each design block and enable individual team members to test their individual

design blocks against the specification for the interface protocol to ease system

integration.

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

74

Related Links

•

System Design with Platform Designer (Standard)

For more information about using Platform Designer (Standard) to improve

your productivity.

•

SOPC Builder User Guide

For more information about SOPC Builder.

2.5 Device Selection

The device you choose affects board specification and layout. Use the following

guidelines for selecting a device.

Choose the device family that best suits your design requirements. Families differ in

cost, performance, logic and memory density, I/O density, power utilization, and

packaging. You must also consider feature requirements, such as I/O standards

support, high-speed transceivers, global or regional clock networks, and the number

of phase-locked loops (PLLs) available in the device.

Each device family has complete documentation, including a data sheet, which

documents device features in detail. You can also see a summary of the resources for

each device in the Device dialog box in the Intel Quartus Prime software.

Carefully study the device density requirements for your design. Devices with more

logic resources and higher I/O counts can implement larger and more complex

designs, but at a higher cost. Smaller devices use lower static power. Select a device

larger than what your design requires if you want to add more logic later in the design

cycle to upgrade or expand your design, and reserve logic and memory for on-chip

debugging. Consider requirements for types of dedicated logic blocks, such as memory

blocks of different sizes, or digital signal processing (DSP) blocks to implement certain

arithmetic functions.

If you have older designs that target an Intel device, you can use their resources as

an estimate for your design. Compile existing designs in the Intel Quartus Prime

software with the Auto device selected by the Fitter option in the Settings dialog

box. Review the resource utilization to learn which device density fits your design.

Consider coding style, device architecture, and the optimization options used in the

Intel Quartus Prime software, which can significantly affect the resource utilization and

timing performance of your design.

Related Links

•

Planning for On-Chip Debugging Tools

 on page 83

For information about on-chip debugging.

•

Product Selector

You can refer to the Altera website to help you choose your device.

•

Selector Guides

You can review important features of each device family in the refer to the

Altera website.

•

Devices and Adapters

For a list of device selection guides.

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

75

•

IP and Megafunctions

For information on how to obtain resource utilization estimates for certain

configurations of Intel’s FPGA IP, refer to the user guides for Intel FPGA

megafunctions and IP MegaCores on the literature page of the Altera website.

2.5.1 Device Migration Planning

Determine whether you want to migrate your design to another device density to allow

flexibility when your design nears completion. You may want to target a smaller (and

less expensive) device and then move to a larger device if necessary to meet your

design requirements. Other designers may prototype their design in a larger device to

reduce optimization time and achieve timing closure more quickly, and then migrate to

a smaller device after prototyping. If you want the flexibility to migrate your design,

you must specify these migration options in the Intel Quartus Prime software at the

beginning of your design cycle.

Selecting a migration device impacts pin placement because some pins may serve

different functions in different device densities or package sizes. If you make pin

assignments in the Intel Quartus Prime software, the Pin Migration View in the Pin

Planner highlights pins that change function between your migration devices.

Related Links
Early Pin Planning and I/O Analysis

 on page 79

2.6 Development Kit Selection

In addition to specifying the device you want to target for compilation, you can also

specify a target board or a development kit for your design.When you select a

development kit, the Intel Quartus Prime software provides a kit reference design, and

creates pin assignments for the kit.

You can select a development kit for your new Intel Quartus Prime project from the
New Project Wizard, or for an existing project by clicking Assignments 

➤

 Device.

2.6.1 Specifying a Development Kit for a New Project

Follow the steps below to select a development kit for a new Intel Quartus Prime

project:
1. To open the New Project Wizard, click File 

➤

 New Project Wizard.

2. Click the Board tab from Family, Device & Board Settings page.
3. Select the Family and Development Kit lists to narrow your board search. The

Available boards table lists all the available boards for the selected Family and

Development Kit type.

4. To view the development kit details for each of the listed boards, click the icons to

the left of the boards in the Available boards table. The Development Kit

Details dialog box appears, displaying all the board details.

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

76

5. Select the desired board from the Available boards table.
6. To set the selected board design as top-level entity, click the Create top-level

design file checkbox. This option automatically sets up the pin assignments for

the selected board. If you choose to uncheck this option, the Intel Quartus Prime

software creates the design for the board and stores the design in

<current_project_dir>/devkits/<design_name>

.

7. Click Finish.

Figure 27.

Selecting the Desired Board from New Project Wizard

Click to open the development

      kit details in a dialog box 

Note: 

If you are unable to find the board you are looking for in the Available Boards table,

click Design Store link at the bottom of the page. This link takes you to the design

store from where you can purchase development kits and download baseline design

examples.

Related Links
Design Store

2.6.2 Specifying a Development Kit for an Existing Project

Follow the steps below to select a development kit for your existing Intel Quartus

Prime project:
1. To open your existing project, click File 

➤

 Open Project.

2. To open the Device Setting Dialog Box, click Assignments 

➤

 Device.

3. Select the desired development kit from the Board tab and click OK.
4. If there are existing pin assignments in your current project, a message box

appears, prompting to remove all location assignments. Click Yes to remove the

Location and I/O Standard pin assignments. The Intel Quartus Prime software

creates the kit's baseline design and stores the design in

<current_project_dir>/devkits/<design_name>

. To retain all your

existing pin assignments, click No.

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

77

Note: 

Repeat the above steps to change the development kit of an existing project.

2.6.3 Setting Pin Assignments

The 

<design_name>

 folder contains the 

platform_setup.tcl file

 that stores all

the pin assignments and the baseline example designs for the board. In addition, the
Intel Quartus Prime software creates a 

.qdf

 file in the 

<current_project_dir>

folder, which stores all the default values for the pin assignments.

To manually set up the pin assignments:
1. Click View 

➤

 Utility Windows 

➤

 Tcl Console.

2. At the Tcl console command prompt, type the command:

source <current_project_dir>/devkits/<design_name>/

platform_setup.tcl

3. At the Tcl console command prompt, type the command:

setup_project

This command populates all assignments available in the 

setup_platform.tcl

file to your 

.qsf

 file.

2.7 Planning for Device Programming or Configuration

System planning includes determining what companion devices, if any, your system

requires. Your board layout also depends on the type of programming or configuration

method you plan to use for programmable devices. Many programming options require

a JTAG interface to connect to the devices, so you might have to set up a JTAG chain

on the board. Additionally, the Intel Quartus Prime software uses the settings for the

configuration scheme, configuration device, and configuration device voltage to enable

the appropriate dual purpose pins as regular I/O pins after you complete

configuration. The Intel Quartus Prime software performs voltage compatibility checks

of those pins during compilation of your design. Use the Configuration tab of the

Device and Pin Options dialog box to select your configuration scheme.

The device family documentation describes the configuration options available for a

device family. For information about programming CPLD devices, refer to your device

documentation.

Related Links
Configuration Handbook

For more details about configuration options.

2.8 Estimating Power

You can use the Intel Quartus Prime power estimation and analysis tools to provide

information to PCB board and system designers. Power consumption in FPGA devices

depends on the design logic, which can make planning difficult. You can estimate

power before you create any source code, or when you have a preliminary version of

the design source code, and then perform the most accurate analysis with the Power

Analyzer when you complete your design.

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

78

You must accurately estimate device power consumption to develop an appropriate

power budget and to design the power supplies, voltage regulators, heat sink, and

cooling system. Power estimation and analysis helps you satisfy two important

planning requirements:
•

Thermal—ensure that the cooling solution is sufficient to dissipate the heat

generated by the device. The computed junction temperature must fall within

normal device specifications.

•

Power supply—ensure that the power supplies provide adequate current to support

device operation.

The Early Power Estimator (EPE) spreadsheet allows you to estimate power utilization

for your design.

You can manually enter data into the EPE spreadsheet, or use the Intel Quartus Prime

software to generate device resource information for your design.

To manually enter data into the EPE spreadsheet, enter the device resources,

operating frequency, toggle rates, and other parameters for your design. If you do not

have an existing design, estimate the number of device resources used in your design,

and then enter the data into the EPE spreadsheet manually.

If you have an existing design or a partially completed design, you can use the Intel
Quartus Prime software to generate the Early Power Estimator File (

.txt

, 

.csv

) to

assist you in completing the EPE spreadsheet.

The EPE spreadsheet includes the Import Data macro that parses the information in

the EPE File and transfers the information into the spreadsheet. If you do not want to

use the macro, you can manually transfer the data into the EPE spreadsheet. For

example, after importing the EPE File information into the EPE spreadsheet, you can

add device resource information. If the existing Intel Quartus Prime project represents

only a portion of your full design, manually enter the additional device resources you

use in the final design.

Estimating power consumption early in the design cycle allows planning of power

budgets and avoids unexpected results when designing the PCB.

When you complete your design, perform a complete power analysis to check the

power consumption more accurately. The Power Analyzer tool in the Intel Quartus

Prime software provides an accurate estimation of power, ensuring that thermal and

supply limitations are met.

Related Links

•

Power Analysis

For more information about power estimation and analysis.

•

Early Power Estimator and Power Analyzer

The EPE spreadsheets for each supported device family are available on the

Altera website.

2.9 Early Pin Planning and I/O Analysis

In many design environments, FPGA designers want to plan the top-level FPGA I/O

pins early to help board designers begin the PCB design and layout. The I/O

capabilities and board layout guidelines of the FPGA device influence pin locations and

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

79

other types of assignments. If the board design team specifies an FPGA pin-out, the

pin locations must be verified in the FPGA placement and routing software to avoid

board design changes.

You can create a preliminary pin-out for an Intel FPGA with the Intel Quartus Prime Pin

Planner before you develop the source code, based on standard I/O interfaces (such

as memory and bus interfaces) and any other I/O requirements for your system. The

Intel Quartus Prime I/O Assignment Analysis checks that the pin locations and

assignments are supported in the target FPGA architecture. You can then use I/O

Assignment Analysis to validate I/O-related assignments that you create or modify

throughout the design process. When you compile your design in the Intel Quartus

Prime software, I/O Assignment Analysis runs automatically in the Fitter to validate

that the assignments meet all the device requirements and generates error messages.

Early in the design process, before creating the source code, the system architect has

information about the standard I/O interfaces (such as memory and bus interfaces),

the IP cores in your design, and any other I/O-related assignments defined by system

requirements. You can use this information with the Early Pin Planning feature in

the Pin Planner to specify details about the design I/O interfaces. You can then create

a top-level design file that includes all I/O information.

The Pin Planner interfaces with the IP core parameter editor, which allows you to

create or import custom IP cores that use I/O interfaces. You can configure how to

connect the functions and cores to each other by specifying matching node names for

selected ports. You can create other I/O-related assignments for these interfaces or

other design I/O pins in the Pin Planner, as described in this section. The Pin Planner

creates virtual pin assignments for internal nodes, so internal nodes are not assigned

to device pins during compilation.

After analysis and synthesis of the newly generated top-level wrapper file, use the

generated netlist to perform I/O Analysis with the Start I/O Assignment Analysis

command.

You can use the I/O analysis results to change pin assignments or IP parameters even

before you create your design, and repeat the checking process until the I/O interface

meets your design requirements and passes the pin checks in the Intel Quartus Prime

software. When you complete initial pin planning, you can create a revision based on

the Intel Quartus Prime-generated netlist. You can then use the generated netlist to

develop the top-level design file for your design, or disregard the generated netlist
and use the generated Intel Quartus Prime Settings File (

.qsf

) with your design.

During this early pin planning, after you have generated a top-level design file, or

when you have developed your design source code, you can assign pin locations and

assignments with the Pin Planner.

With the Pin Planner, you can identify I/O banks, voltage reference (VREF) groups, and

differential pin pairings to help you through the I/O planning process. If you selected a

migration device, the Pin Migration View highlights the pins that have changed

functions in the migration device when compared to the currently selected device.

Selecting the pins in the Device Migration view cross-probes to the rest of the Pin

Planner, so that you can use device migration information when planning your pin

assignments. You can also configure board trace models of selected pins for use in

“board-aware” signal integrity reports generated with the Enable Advanced I/O

Timing option . This option ensures that you get accurate I/O timing analysis. You can

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

80

use a Microsoft Excel spreadsheet to start the I/O planning process if you normally use

a spreadsheet in your design flow, and you can export a Comma-Separated Value File
(

.csv

) containing your I/O assignments for spreadsheet use when you assign all pins.

When you complete your pin planning, you can pass pin location information to PCB

designers. The Pin Planner is tightly integrated with certain PCB design EDA tools, and

can read pin location changes from these tools to check suggested changes. Your pin

assignments must match between the Intel Quartus Prime software and your

schematic and board layout tools to ensure the FPGA works correctly on the board,

especially if you must make changes to the pin-out. The system architect uses the

Intel Quartus Prime software to pass pin information to team members designing

individual logic blocks, allowing them to achieve better timing closure when they

compile their design.

Start FPGA planning before you complete the HDL for your design to improve the

confidence in early board layouts, reduce the chance of error, and improve the overall

time to market of the design. When you complete your design, use the Fitter reports

for the final sign-off of pin assignments. After compilation, the Intel Quartus Prime
software generates the Pin-Out File (

.pin

), and you can use this file to verify that

each pin is correctly connected in board schematics.

Related Links

•

Device Migration Planning

 on page 76

•

Set Up Top-Level Design File Window (Edit Menu)

For more information about setting up the nodes in your design, refer to Intel

Quartus Prime Help.

•

I/O Management

For more information about I/O assignment and analysis.

•

Mentor Graphics PCB Design Tools Support

•

Cadence PCB Design Tools Support

For more information about passing I/O information between the Intel Quartus

Prime software and third-party EDA tools.

2.9.1 Simultaneous Switching Noise Analysis

Simultaneous switching noise (SSN) is a noise voltage inducted onto a victim I/O pin

of a device due to the switching behavior of other aggressor I/O pins in the device.

Intel provides tools for SSN analysis and estimation, including SSN characterization

reports, an Early SSN Estimator (ESE) spreadsheet tool, and the SSN Analyzer in the

Intel Quartus Prime software. SSN often leads to the degradation of signal integrity by

causing signal distortion, thereby reducing the noise margin of a system. You must

address SSN with estimation early in your system design, to minimize later board

design changes. When your design is complete, verify your board design by

performing a complete SSN analysis of your FPGA in the Intel Quartus Prime software.

Related Links

•

Altera’s Signal Integrity Center

For more information and device support for the ESE spreadsheet tool on the

Altera website.

•

Simultaneous Switching Noise (SSN

For more information about the SSN Analyzer.

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

81

2.10 Selecting Third-Party EDA Tools

Your complete FPGA design flow may include third-party EDA tools in addition to the

Intel Quartus Prime software. Determine which tools you want to use with the Intel

Quartus Prime software to ensure that they are supported and set up properly, and

that you are aware of their capabilities.

2.10.1 Synthesis Tool

You can use supported standard third-party EDA synthesis tools to synthesize your

Verilog HDL or VHDL design, and then compile the resulting output netlist file in the

Intel Quartus Prime software. The Intel Quartus Prime Standard Edition software

includes integrated synthesis that supports Verilog HDL, VHDL, Altera Hardware

Description Language (AHDL), and schematic design entry.

Different synthesis tools may give different results for each design. To determine the

best tool for your application, you can experiment by synthesizing typical designs for

your application and coding style. Perform placement and routing in the Intel Quartus

Prime software to get accurate timing analysis and logic utilization results.

The synthesis tool you choose may allow you to create a Intel Quartus Prime project

and pass constraints, such as the EDA tool setting, device selection, and timing

requirements that you specified in your synthesis project. You can save time when

setting up your Intel Quartus Prime project for placement and routing.

Tool vendors frequently add new features, fix tool issues, and enhance performance

for Intel devices, you must use the most recent version of third-party synthesis tools.

2.10.2 Simulation Tool

Intel provides the Mentor Graphics ModelSim - Intel FPGA Edition with the Intel

Quartus Prime software. You can also purchase the ModelSim - Intel FPGA Edition or a

full license of the ModelSim software to support large designs and achieve faster

simulation performance. The Intel Quartus Prime software can generate both

functional and timing netlist files for ModelSim and other third-party simulators.

Use the simulator version that your Intel Quartus Prime software version supports for

best results. You must also use the model libraries provided with your Intel Quartus

Prime software version. Libraries can change between versions, which might cause a

mismatch with your simulation netlist.

2.10.3 Formal Verification Tools

Consider whether the Intel Quartus Prime software supports the formal verification

tool that you want to use, and whether the flow impacts your design and compilation

stages of your design.

Using a formal verification tool can impact performance results because performing

formal verification requires turning off certain logic optimizations, such as register

retiming, and forces you to preserve hierarchy blocks, which can restrict optimization.

Formal verification treats memory blocks as black boxes. Therefore, you must keep

memory in a separate hierarchy block so other logic does not get incorporated into the

black box for verification. If formal verification is important to your design, plan for

limitations and restrictions at the beginning of the design cycle rather than make

changes later.

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

82

2.11 Planning for On-Chip Debugging Tools

Evaluate on-chip debugging tools early in your design process, Making changes to

include debugging tools further in the design process is more time consumming and

error prone.

In-system debugging tools offer different advantages and trade-offs. A particular

debugging tool may work better for different systems and designers. Consider the

following debugging requirements when you plan your design:
•

JTAG connections—required to perform in-system debugging with JTAG tools. Plan

your system and board with JTAG ports that are available for debugging.

•

Additional logic resources (ALR)—required to implement JTAG hub logic. If you set

up the appropriate tool early in your design cycle, you can include these device

resources in your early resource estimations to ensure that you do not overload

the device with logic.

•

Reserve device memory—required if your tool uses device memory to capture data

during system operation. To ensure that you have enough memory resources to

take advantage of this debugging technique, consider reserving device memory to

use during debugging.

•

Reserve I/O pins—required if you use the Logic Analyzer Interface (LAI) or Signal

Probe tools, which require I/O pins for debugging. If you reserve I/O pins for

debugging, you do not have to later change your design or board. The LAI can

multiplex signals with design I/O pins if required. Ensure that your board supports

a debugging mode, in which debugging signals do not affect system operation.

•

Instantiate an IP core in your HDL code—required if your debugging tool uses an

Intel FPGA IP core.

•

Instantiate the Signal Tap Logic Analyzer IP core—required if you want to manually

connect the Signal Tap Logic Analyzer to nodes in your design and ensure that the

tapped node names do not change during synthesis.
Note: You can add the Signal Tap Logic Analyzer as a separate design partition for

incremental compilation to minimize recompilation times.

Table 13.

Factors to Consider When Using Debugging Tools During Design Planning

Stages

Design Planning Factor

Signal

Tap

Logic

Analyzer

System

Console

In-

System

Memory

Content

Editor

Logic

Analyzer

Interface

(LAI)

Signal

Probe

In-

System

Sources

and

Probes

Virtual

JTAG IP

Core

JTAG connections

Yes

Yes

Yes

Yes

—

Yes

Yes

Additional logic resources

—

Yes

—

—

—

—

Yes

Reserve device memory

Yes

Yes

—

—

—

—

—

Reserve I/O pins

—

—

—

Yes

Yes

—

—

Instantiate IP core in your HDL code

—

—

—

—

—

Yes

Yes

Related Links

•

System Debugging Tools Overview

In Intel Quartus Prime Standard Edition Handbook Volume 3

2 Design Planning with the Intel Quartus Prime Software

QPS5V1 | 2017.10.06

Intel

®

 Quartus

®

 Prime Standard Edition Handbook Volume 1 Design and Synthesis

83