Description
Alliance Semiconductor AS7C164-20JC Fast Asynchronous, 64K, 8Kx8 5V
AS7C164 (5V version)· Commercial temperature· Organization: 8,192 words × 8 bits· Center power and ground pins· High speed 12/15/20 ns address access time 6/7/8 ns output enable access time· Low power consumption: ACTIVE (AS7C164) / max 12 ns
The is a high performance CMOS 65,536-bit Static Random Access Memory (SRAM) device organized as 8,192 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) 12/15/20 ns with output enable access times (tOE) 6/7/8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory systems. When CE1 is High CE2 is Low the device enters standby mode. The standard AS7C164 is guaranteed not to exceed 11.0 mW power consumption in standby mode, and typically requires only 250 µW; it offers 2.0V data retention with maximum power of 120 µW. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C164 is packaged in 300 mil SOJ packages.
Manufacturer:Electronic Components
Datasheet:Others/AS7C164-20JC.pdf
