Description
CXDQ3BFAM-CQ-A CXMT Memory DDR4 SDRAM 8Gbit 1.14V~1.26V 1.333GHz 105.8mA Auto precharge function;Asynchronous reset function;Dynamic on chip termination;Data mask function;CRC function;ZQ calibration function BGA-96(13×7.5)
Key Features
• Power supply : VDD = VDDQ = 1.2V (1.14V to 1.26V); VPP = 2.5V (2.375V to 2.75V)
• JEDEC standard package: x16 96-ball FBGA
• Array Configuration : 8 banks (x16) 2 groups of 4 banks
• 8n-bit prefetch architecture
• Burst Length (BL) : 8 and 4 with Burst Chop (BC)
• Programmable CAS Latency (CL)
• Programmable CAS Write Latency (CWL)
• Internal generated Vref for data inputs
• On-Die Termination (ODT) : support Nominal, Park and Dynamic ODT
• Differential clock and data strobe inputs (CK_t ,CK_c; DQS_t, DQS_c)
• Interface: 1.2V Pseudo Open Drain (POD) IO
• Per DRAM Addressability (PDA)
• Data Bus Inversion (DBI)
• Data Mask (DM) for write data
• Maximum Power Saving Mode (MPSM)
• Programmable Partial Array Self-Refresh (PASR)
• Asynchronous reset for power up
• Precharge: auto precharge option for each burst access
• Operating case temperature : 0°C ≤ TCase ≤ 95°C
• Support auto-refresh and self-refresh mode
Datasheet: CXMT CXDQ3BFAM-CQ-A
