Description
H5AN8G6NAFR-UHC Hynix DDR4 SDRAM 8Gbit 1.14V~1.26V 46mA 1.2GHz FBGA-96, Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Dynamic on-chip termination;ZQ calibration function;CRC function;Write leveling function.
The H5AN8G4NAFR-xxC, H5AN8G8NAFR-xxC and H5AN8G6NAFR-xxC are a 8Gb CMOS Double Data Rate
IV (DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memory
density and high bandwidth. SK hynix 8Gb DDR4 SDRAMs offer fully synchronous operations referenced
to both rising and falling edges of the clock. While all addresses and control inputs are latched on
the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.
Basic Features
Memory Capacity: 8Gb (512M x 16-bit organization).
Operating Voltage: VDD = VDDQ = 1.2V ± 0.06V.
Clock Operation: Fully synchronous operations referenced to both rising and falling edges of the clock.
Data Rate: 1200 MHz.
CAS Latency: Programmable CAS latency ranging from 9 to 20.
Packaging and Environmental Compliance
Package Type: 96-ball FBGA (Fine Ball Grid Array).
Environmental Compliance: Lead-free and halogen-free, RoHS compliant.
Additional Features
Internal Pipelining: Data paths are internally pipelined with 8-bit prefetch to achieve high bandwidth.
Refresh Cycle: Average refresh cycle of 7.8 μs at 0°C to 85°C and 3.9 μs at 85°C to 95°C.
Power Saving Modes: Supports Maximum Power Saving Mode and Low Power Auto Self Refresh (LP ASR) mode.
Other Functionalities: Supports features like Write CRC, ZQ calibration, and Dynamic On Die Termination.
FEATURES
• VDD=VDDQ=1.2V +/- 0.06V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS latency 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19 and 20 supported
• Programmable additive latency 0, CL-1, and CL-2
supported (x4/x8 only)
• Programmable CAS Write latency (CWL) = 9, 10, 11,
12, 14, 16, 18
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 16banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
– 7.8 μs at 0oC ~ 85 oC
– 3.9 μs at 85oC ~ 95 oC
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)
• Driver strength selected by MRS
• Dynamic On Die Termination supported
• Two Termination States such as RTT_PARK and
RTT_NOM switchable by ODT pin
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
• This product in compliance with the RoHS directive.
• Internal Vref DQ level generation is available
• Write CRC is supported at all speed grades
• Maximum Power Saving Mode is supported
• TCAR(Temperature Controlled Auto Refresh) mode is
supported
• LP ASR(Low Power Auto Self Refresh) mode is supported
• Fine Granularity Refresh is supported
• Per DRAM Addressability is supported
• Geardown Mode(1/2 rate, 1/4 rate) is supported
• Programable Preamble for read and write is supported
• Self Refresh Abort is supported
• CA parity (Command/Address Parity) mode is supported
• Bank Grouping is applied, and CAS to CAS latency
(tCCD_L, tCCD_S) for the banks in the same or different
bank group accesses are available
• DBI(Data Bus Inversion) is supported(x8)
Memory Size: 8Gbit DDR4 SDRAM
Voltage – Supply: 1.14V~1.26V
Clock Frequency: 1.2GHz
Packaging: Tray
Manufacturer PN: H5AN8G6NAFR-UHC
Manufacturer: HYNIX
